公开(公告)号：US11256657B2

公开(公告)日：2022-02-22

申请号：US16364619

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Tejpal Singh ,  Yedidya Hilewitz ,  Ankush Varma ,  Yen-Cheng Liu ,  Krishnakanth V. Sistla ,  Jeffrey Chamberlain

IPC: G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  G06F9/54 ,  G06F9/30 ,  G06F1/3296 ,  G06F1/3234

Abstract: In one embodiment, an apparatus includes an interconnect to couple a plurality of processing circuits. The interconnect may include a pipe stage circuit coupled between a first processing circuit and a second processing circuit. This pipe stage circuit may include: a pipe stage component having a first input to receive a signal via the interconnect and a first output to output the signal; and a selection circuit having a first input to receive the signal from the first output of the pipe stage component and a second input to receive the signal via a bypass path, where the selection circuit is dynamically controllable to output the signal received from the first output of the pipe stage component or the signal received via the bypass path. Other embodiments are described and claimed.

公开(公告)号：US20150186191A1

公开(公告)日：2015-07-02

申请号：US14142137

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Bahaa Fahim ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

IPC: G06F9/52 ,  G06F12/08

CPC classification number: G06F9/524 ,  G06F12/0815 ,  G06F12/0855

Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.

Abstract translation: 这里公开了一种用于防止处理器中的死锁的缓存代理。 缓存代理包括被配置为从处理器的核心接收请求的接收器。 缓存代理包括耦合到接收器的入口逻辑，以确定请求潜在地是可缓存的请求。 入口逻辑是确定请求不会耗尽可用的一致性资源。 入口逻辑是允许响应于该请求不消耗可用的一致性资源的确定来处理该请求。

公开(公告)号：US09189296B2

公开(公告)日：2015-11-17

申请号：US14142137

申请日：2013-12-27

Applicant: INTEL CORPORATION

Inventor： Bahaa Fahim ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

IPC: G06F15/00 ,  G06F9/52 ,  G06F12/08

CPC classification number: G06F9/524 ,  G06F12/0815 ,  G06F12/0855

Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.

Abstract translation: 这里公开了一种用于防止处理器中的死锁的缓存代理。 缓存代理包括被配置为从处理器的核心接收请求的接收器。 缓存代理包括耦合到接收器的入口逻辑，以确定请求潜在地是可缓存的请求。 入口逻辑是确定请求不会耗尽可用的一致性资源。 入口逻辑是允许响应于该请求不消耗可用的一致性资源的确定来处理该请求。