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    Core tightly coupled lockstep for high functional safety
    3.
    发明授权
    Core tightly coupled lockstep for high functional safety 有权

    公开(公告)号：US10946866B2

    公开(公告)日：2021-03-16

    申请号：US15942466

    申请日：2018-03-31

    Applicant: Intel Corporation

    Inventor： Bahaa Fahim ,  Riccardo Mariani ,  Dean Mulla ,  Robert Gottlieb

    IPC: B60W50/023 ,  B60W50/02 ,  B60R16/023 ,  B60W50/00

    Abstract: Methods and apparatus relating to provision of core tightly coupled lockstep for high functional safety are described. In an embodiment, a master core, coupled to a slave core, executes one or more operations to support Advanced Driver Assistance Systems (ADA) or autonomous driving. The master core and the slave core receive the same input signal and core tightly couple logic causes generation of a signal in response to comparison of a first output from the master core and a second output from the slave core. The generated signal causes an interruption of the one or more operations in response to a mismatch between the first output and the second output. Other embodiments are also disclosed and claimed.

    Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory
    5.
    发明授权
    Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory 有权
    本地缓存行的包含和非包容性跟踪，以避免缓存行内存上的近似存储器读取写入两级系统内存

    公开(公告)号：US09418009B2

    公开(公告)日：2016-08-16

    申请号：US14142045

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0888

    Abstract: A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.

    Abstract translation: 处理器可以包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理器可以包括逻辑电路，以使存储器控制器确定写入请求是远程生成还是本地生成，并且当写入请求被远程生成以指示存储器控制器在执行写入之前执行近似存储器的读取，当写入 请求在本地生成，并且由写入请求所针对的高速缓存行处于包含状态，以指示存储器控制器执行写入而不执行近似存储器的读取，并且当本地生成写入请求时， 写请求处于非包容状态，以指示存储器控制器在执行写操作之前读取存储器。

    Caching agent for deadlock prevention in a processor by allowing requests that do not deplete available coherence resources
    6.
    发明授权
    Caching agent for deadlock prevention in a processor by allowing requests that do not deplete available coherence resources 有权
    通过允许不消耗可用的一致性资源的请求，处理器中的缓存代理程序可以防止死锁

    公开(公告)号：US09189296B2

    公开(公告)日：2015-11-17

    申请号：US14142137

    申请日：2013-12-27

    Applicant: INTEL CORPORATION

    Inventor： Bahaa Fahim ,  Jeffrey Chamberlain ,  Yen-Cheng Liu

    IPC: G06F15/00 ,  G06F9/52 ,  G06F12/08

    CPC classification number: G06F9/524 ,  G06F12/0815 ,  G06F12/0855

    Abstract: Disclosed herein is a caching agent for preventing deadlock in a processor. The caching agent includes a receiver configured to receive a request from a core of the processor. The caching agent includes ingress logic coupled to the receiver to determine that the request is potentially a cacheable request. The ingress logic is to determine that the request does not deplete an available coherence resource. The ingress logic is to allow the request to be processed in response to the determination that the request does not deplete the available coherence resource.

    Abstract translation: 这里公开了一种用于防止处理器中的死锁的缓存代理。 缓存代理包括被配置为从处理器的核心接收请求的接收器。 缓存代理包括耦合到接收器的入口逻辑，以确定请求潜在地是可缓存的请求。 入口逻辑是确定请求不会耗尽可用的一致性资源。 入口逻辑是允许响应于该请求不消耗可用的一致性资源的确定来处理该请求。

    Method and system for cache agent trace and capture
    8.
    发明授权
    Method and system for cache agent trace and capture 有权

    公开(公告)号：US11281562B2

    公开(公告)日：2022-03-22

    申请号：US16721868

    申请日：2019-12-19

    Applicant: Intel Corporation

    Inventor： Bahaa Fahim ,  Swadesh Choudhary

    IPC: G06F11/30 ,  G06F11/34 ,  G06F11/14 ,  G06F11/36 ,  G06F11/07

    Abstract: In one embodiment, a processor comprises a fabric interconnect to couple a first cache agent to at least one of a memory controller or an input/output (I/O) controller; and a first cache agent comprising a cache controller coupled to a cache; and a trace and capture engine to periodically capture a snapshot of state information associated with the first cache agent; trace events to occur at the first cache agent in between captured snapshots; and send the captured snapshots and traced events via the fabric interconnect to the memory controller or I/O controller for storage at a system memory or storage device.

    Integrated input/output management
    9.
    发明授权
    Integrated input/output management 有权

    公开(公告)号：US10860515B2

    公开(公告)日：2020-12-08

    申请号：US16014012

    申请日：2018-06-21

    Applicant: Intel Corporation

    Inventor： Swadesh Choudhary ,  Bahaa Fahim ,  Mahesh Wagh

    IPC: G06F11/00 ,  G06F13/40 ,  G06F11/07 ,  G06F13/42 ,  G06F11/10 ,  G06F11/18

    Abstract: Herein is disclosed an integrated input/output (“I/O”) processing system, comprising an I/O port, configured to receive I/O data and to deliver the I/O data to one or more processors; one or more processors, further comprising a first processing logic and a second processing logic, wherein the one or more processors are configured to deliver the received I/O data to the first processing logic and to the second processing logic, and wherein the first processing logic and the second processing logic are configured to redundantly process the I/O data; and a comparator, configured to compare an output of the first processing logic and an output of the second processing logic.

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