公开(公告)号：US09548937B2

公开(公告)日：2017-01-17

申请号：US14139512

申请日：2013-12-23

Applicant: INTEL CORPORATION

Inventor： Keith Hazelet ,  Ziv Kfir ,  Christopher Thornburg ,  Barak Hermesh

IPC: H04J3/02 ,  H04L12/835 ,  H04L12/801 ,  H04L12/863

CPC classification number: H04L47/30 ,  H04L47/29 ,  H04L47/621

Abstract: Techniques are disclosed for controlling data transmission in multi-stream digital systems. The techniques disclosed allow an input stream to a conditional access system to be throttled when a FIFO begins to fill up. Each data stream may have its own FIFO, which sends data to a MUX and exports its status to a backpressure rate control module. Multiple seconds worth of data may be stored in a BPRC buffer ahead of the backpressure rate control module prior to being transmitted to a MUX FIFO buffer. The backpressure rate control module may use the cached data to fill available spaces within a MUX FIFO buffer. The determination to forward a data packet may be based on the individual MUX FIFO buffer levels, the sum of all the MUX FIFO buffer levels, and/or one or more configurable threshold values. In some embodiments, individual thresholds may be assigned to each FIFO buffer.

Abstract translation: 公开了用于控制多流数字系统中的数据传输的技术。 当FIFO开始填充时，所公开的技术允许对条件访问系统的输入流进行限制。 每个数据流可以具有其自己的FIFO，其将数据发送到MUX并将其状态导出到背压速率控制模块。 在发送到MUX FIFO缓冲器之前，可将多秒数据的数据存储在背压速率控制模块之前的BPRC缓冲器中。 背压速率控制模块可以使用缓存的数据来填充MUX FIFO缓冲器内的可用空间。 转发数据分组的确定可以基于各个MUX FIFO缓冲器级别，所有MUX FIFO缓冲器级别的总和和/或一个或多个可配置的阈值。 在一些实施例中，可以将各个阈值分配给每个FIFO缓冲器。