公开(公告)号：US20140237303A1

公开(公告)日：2014-08-21

申请号：US13997664

申请日：2011-12-23

Applicant: INTEL CORPORATION

Inventor： Jayashankar Bharadwaj ,  Victor W. Lee ,  Kim Daehyun ,  Nalini Vasudevan ,  Tin-Fook Ngai ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043

Abstract: An apparatus and method are described for detecting and responding to fault conditions in a processor. For example, one embodiment of a method comprises: reading each active element in succession from a first vector register, each active element specifying an address for a gather or load operation; detecting one or more fault conditions associated with one or more of the active elements; for each active element read in succession prior to a detected fault condition on an element other than the first active element, storing the data loaded from an address associated with the active element in a first output vector register; and for each active element associated with the detected fault condition and following the detected fault condition, setting a bit in an output mask register to indicate the detected fault condition.

Abstract translation: 描述了用于检测和响应处理器中的故障状况的装置和方法。 例如，一种方法的一个实施例包括：从第一向量寄存器连续读取每个有源元件，每个有源元件指定用于集合或加载操作的地址; 检测与一个或多个所述有源元件相关联的一个或多个故障状况; 对于在除了所述第一有源元件之外的元件的检测到的故障状况之前连续读取的每个有源元件，将从与所述有源元件相关联的地址加载的数据存储在第一输出向量寄存器中; 并且对于与检测到的故障状况相关联的每个有源元件并且跟随检测到的故障状况，设置输出屏蔽寄存器中的位以指示检测到的故障状况。