公开(公告)号：US10884957B2

公开(公告)日：2021-01-05

申请号：US16160952

申请日：2018-10-15

Applicant: Intel Corporation

Inventor： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor W. Lee ,  Abhishek Sharma ,  Huseyin E. Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  Ian Young

IPC: G06F13/16 ,  G06F13/28 ,  G06N20/00

Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

公开(公告)号：US20170242700A1

公开(公告)日：2017-08-24

申请号：US15426963

申请日：2017-02-07

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Jong Soo Park

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38 ,  G06F12/084 ,  G06F12/0815

CPC classification number: G06F9/30043 ,  G06F9/30036 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/621 ,  Y02D10/13

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

公开(公告)号：US09690716B2

公开(公告)日：2017-06-27

申请号：US14621654

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Sheng Li ,  Sanjay Kumar ,  Victor W. Lee ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor

IPC: G06F12/08 ,  G06F12/1045 ,  G06F12/0891

CPC classification number: G06F12/1045 ,  G06F9/467 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/69

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.

公开(公告)号：US09076254B2

公开(公告)日：2015-07-07

申请号：US14054933

申请日：2013-10-16

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Mikhail Smelyanskiy ,  Ganesh S. Dasika ,  Jose Gonzalez ,  Jatin Chhugani ,  Yen-Kuang Chen ,  Changkyu Kim ,  Julio Gago ,  Santiago Galan ,  Victor Moya Del Barrio

IPC: G09G5/00 ,  G06T11/00 ,  G06F17/16 ,  G06T1/00

CPC classification number: G06T11/001 ,  G06F17/16 ,  G06T1/00

Abstract: A texture unit may be used to perform general purpose mathematical computations such as dot products. This enables some general purpose computations and operations to be offloaded from a central processing unit to the texture unit. The texture unit may use linear interpolators in order to perform the dot product calculations.

Abstract translation: 纹理单元可用于执行诸如点积的通用数学计算。 这使得一些通用计算和操作能够从中央处理单元卸载到纹理单元。 纹理单元可以使用线性内插器来执行点积计算。

公开(公告)号：US20130297878A1

公开(公告)日：2013-11-07

申请号：US13934198

申请日：2013-07-02

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Yen-Kuang Chen ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Anthony-Trung D. Nguyen ,  Nadathur Rajagopalan Satish

IPC: G06F12/08

CPC classification number: G06F12/0811 ,  G06F9/30043 ,  G06F12/0802 ,  G06F12/0897 ,  G06F2212/62 ,  Y02D10/13

Abstract: Methods and apparatus relating to gather or scatter operations in a multi-level cache are described. In some embodiments, a logic may determine whether to perform gather or scatter operations at a first memory or a second memory, based in part on a relative performance of performing the gather or scatter operations at the first memory and the second memory. Other embodiments are also described and claimed.

Abstract translation: 描述与多级缓存中的收集或散布操作有关的方法和装置。 在一些实施例中，逻辑可以部分地基于在第一存储器和第二存储器执行收集或散布操作的相对性能来确定是否在第一存储器或第二存储器执行收集或散布操作。 还描述和要求保护其他实施例。

公开(公告)号：US10775873B2

公开(公告)日：2020-09-15

申请号：US16288580

申请日：2019-02-28

Applicant: Intel Corporation

Inventor： Victor W. Lee ,  Edward T. Grochowski ,  Daehyun Kim ,  Yuxin Bai ,  Sheng Li ,  Naveen K. Mellempudi ,  Dhiraj D. Kalamkar

IPC: G06F1/00 ,  G06F1/3287 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3225 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/50

Abstract: In an embodiment, a processor includes: a plurality of first cores to independently execute instructions, each of the plurality of first cores including a plurality of counters to store performance information; at least one second core to perform memory operations; and a power controller to receive performance information from at least some of the plurality of counters, determine a workload type executed on the processor based at least in part on the performance information, and based on the workload type dynamically migrate one or more threads from one or more of the plurality of first cores to the at least one second core for execution during a next operation interval. Other embodiments are described and claimed.

公开(公告)号：US09921832B2

公开(公告)日：2018-03-20

申请号：US13993653

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Albert Hartono ,  Jayashankar Bharadwaj ,  Nalini Vasudevan ,  Sara S. Baghsorkhi ,  Victor W. Lee ,  Daehyun Kim

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30065 ,  G06F9/3455

Abstract: A vector reduction instruction with non-unit strided access pattern is received and executed by the execution circuitry of a processor. In response to the instruction, the execution circuitry performs an associative reduction operation on data elements of a first vector register. Based on values of the mask register and a current element position being processed, the execution circuitry sequentially sets one or more data elements of the first vector register to a result, which is generated by the associative reduction operation applied to both a previous data element of the first vector register and a data clement of a third vector register. The previous data element is located more than one element position away from the current element position.

公开(公告)号：US09898266B2

公开(公告)日：2018-02-20

申请号：US15005781

申请日：2016-01-25

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Jayashankar Bharadwaj ,  Christopher J. Hughes ,  Milind B. Girkar ,  Mark J. Charney ,  Robert Valentine ,  Victor W. Lee ,  Daehyun Kim ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F8/452 ,  G06F8/70 ,  G06F9/30036 ,  G06F9/38 ,  G06F9/3836

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes prior to executing an original loop having iterations, analyzing, via a processor, the iterations of the original loop, identifying a dependency between a first one of the iterations of the original loop and a second one of the iterations of the original loop, after identifying the dependency, vectorizing a first group of the iterations of the original loop based on the identified dependency to form a vectorization loop, and setting a dynamic adjustment value of the vectorization loop based on the identified dependency.

公开(公告)号：US09690552B2

公开(公告)日：2017-06-27

申请号：US14583657

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Hongbo Rong ,  Peng Tu ,  Tatiana Shpeisman ,  Hai Liu ,  Todd A. Anderson ,  Youfeng Wu ,  Paul M. Petersen ,  Victor W. Lee ,  P. G. Lowney ,  Arch D. Robison ,  Cheng Wang

IPC: G06F9/44 ,  G06F9/45

CPC classification number: G06F8/43 ,  G06F8/31 ,  G06F8/443 ,  G06F8/4441 ,  G06F8/453 ,  G06F8/49 ,  G06F8/54

Abstract: Technologies for generating composable library functions include a first computing device that includes a library compiler configured to compile a composable library and second computing device that includes an application compiler configured to compose library functions of the composable library based on a plurality of abstractions written at different levels of abstractions. For example, the abstractions may include an algorithm abstraction at a high level, a blocked-algorithm abstraction at medium level, and a region-based code abstraction at a low level. Other embodiments are described and claimed herein.

公开(公告)号：US09563425B2

公开(公告)日：2017-02-07

申请号：US13687918

申请日：2012-11-28

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Changkyu Kim ,  Daehyun Kim ,  Victor W. Lee ,  Jong Soo Park

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/44 ,  G06F9/38 ,  G06F12/08 ,  G06F9/54

CPC classification number: G06F9/30043 ,  G06F9/30036 ,  G06F9/30185 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3887 ,  G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/621 ,  Y02D10/13

Abstract: Instructions and logic provide pushing buffer copy and store functionality. Some embodiments include a first hardware thread or processing core, and a second hardware thread or processing core, a cache to store cache coherent data in a cache line for a shared memory address accessible by the second hardware thread or processing core. Responsive to decoding an instruction specifying a source data operand, said shared memory address as a destination operand, and one or more owner of said shared memory address, one or more execution units copy data from the source data operand to the cache coherent data in the cache line for said shared memory address accessible by said second hardware thread or processing core in the cache when said one or more owner includes said second hardware thread or processing core.

Abstract translation: 说明和逻辑提供推送缓冲区复制和存储功能。 一些实施例包括第一硬件线程或处理核心，以及第二硬件线程或处理核心，高速缓存，用于存储由第二硬件线程或处理核心可访问的共享存储器地址的高速缓存行中的高速缓存相干数据。 响应于对指定源数据操作数，所述共享存储器地址作为目的地操作数的指令以及所述共享存储器地址的一个或多个所有者进行解码，一个或多个执行单元将数据从源数据操作数复制到高速缓存一致数据 当所述一个或多个所有者包括所述第二硬件线程或处理核心时，由所述第二硬件线程或高速缓存中的处理核心访问的所述共享存储器地址的高速缓存行。