公开(公告)号：US20160154638A1

公开(公告)日：2016-06-02

申请号：US15018445

申请日：2016-02-08

Applicant: Intel Corporation

Inventor： Jayashankar Bharadwaj ,  Nalini Vasudevan ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45

CPC classification number: G06F8/4441 ,  G06F8/443 ,  G06F8/452 ,  G06F9/06 ,  G06F9/30 ,  G06F9/44

Abstract: Methods and systems to convert a scalar computer program loop having loop-carried dependences into a vector computer program loop are disclosed. One such method includes, replacing the scalar recurrence operation in the scalar computer program loop with a first vector summing operation and a first vector recurrence operation. The first vector summing operation is to generate a first running sum and the first vector recurrence operation is to generate a first vector. In some examples, the first vector recurrence operation is based on the scalar recurrence operation. Disclosed methods also include inserting: 1) a renaming operation to rename the first vector, 2) a second vector summing operation that is to generate a second running sum; and 3) a second vector recurrence operation to generate a second vector based on the renamed first vector.

Abstract translation: 公开了将具有循环携带依赖性的标量计算机程序循环转换为向量计算机程序循环的方法和系统。 一种这样的方法包括用第一矢量求和操作和第一矢量再现操作来代替标量计算机程序循环中的标量重复运算。 第一矢量求和运算是产生第一运行和，第一矢量再现运算是产生第一矢量。 在一些示例中，第一个矢量复现操作基于标量重复操作。 所公开的方法还包括插入：1）重命名操作以重命名第一向量，2）第二向量求和操作，用于生成第二运行和; 以及3）第二矢量再现操作，以基于所述重命名的第一矢量生成第二矢量。

公开(公告)号：US09921832B2

公开(公告)日：2018-03-20

申请号：US13993653

申请日：2012-12-28

Applicant: Intel Corporation

Inventor： Albert Hartono ,  Jayashankar Bharadwaj ,  Nalini Vasudevan ,  Sara S. Baghsorkhi ,  Victor W. Lee ,  Daehyun Kim

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30065 ,  G06F9/3455

Abstract: A vector reduction instruction with non-unit strided access pattern is received and executed by the execution circuitry of a processor. In response to the instruction, the execution circuitry performs an associative reduction operation on data elements of a first vector register. Based on values of the mask register and a current element position being processed, the execution circuitry sequentially sets one or more data elements of the first vector register to a result, which is generated by the associative reduction operation applied to both a previous data element of the first vector register and a data clement of a third vector register. The previous data element is located more than one element position away from the current element position.

公开(公告)号：US09898266B2

公开(公告)日：2018-02-20

申请号：US15005781

申请日：2016-01-25

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Jayashankar Bharadwaj ,  Christopher J. Hughes ,  Milind B. Girkar ,  Mark J. Charney ,  Robert Valentine ,  Victor W. Lee ,  Daehyun Kim ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45 ,  G06F9/44 ,  G06F9/38 ,  G06F9/30

CPC classification number: G06F8/443 ,  G06F8/433 ,  G06F8/452 ,  G06F8/70 ,  G06F9/30036 ,  G06F9/38 ,  G06F9/3836

Abstract: Loop vectorization methods and apparatus are disclosed. An example method includes prior to executing an original loop having iterations, analyzing, via a processor, the iterations of the original loop, identifying a dependency between a first one of the iterations of the original loop and a second one of the iterations of the original loop, after identifying the dependency, vectorizing a first group of the iterations of the original loop based on the identified dependency to form a vectorization loop, and setting a dynamic adjustment value of the vectorization loop based on the identified dependency.

公开(公告)号：US09733913B2

公开(公告)日：2017-08-15

申请号：US15018445

申请日：2016-02-08

Applicant: Intel Corporation

Inventor： Jayashankar Bharadwaj ,  Nalini Vasudevan ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/45 ,  G06F9/06 ,  G06F9/30 ,  G06F9/44

CPC classification number: G06F8/4441 ,  G06F8/443 ,  G06F8/452 ,  G06F9/06 ,  G06F9/30 ,  G06F9/44

Abstract: Methods and systems to convert a scalar computer program loop having loop-carried dependences into a vector computer program loop are disclosed. One such method includes, replacing the scalar recurrence operation in the scalar computer program loop with a first vector summing operation and a first vector recurrence operation. The first vector summing operation is to generate a first running sum and the first vector recurrence operation is to generate a first vector. In some examples, the first vector recurrence operation is based on the scalar recurrence operation. Disclosed methods also include inserting: 1) a renaming operation to rename the first vector, 2) a second vector summing operation that is to generate a second running sum; and 3) a second vector recurrence operation to generate a second vector based on the renamed first vector.

公开(公告)号：US09588814B2

公开(公告)日：2017-03-07

申请号：US14582430

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sara S. Baghsorkhi ,  Albert Hartono ,  Youfeng Wu ,  Cheng Wang

IPC: G06F7/02 ,  H03M13/00 ,  G06F9/50 ,  G06F9/30

CPC classification number: G06F9/50 ,  G06F9/30 ,  G06F9/3834 ,  G06F9/3838

Abstract: The present disclosure is directed to fast approximate conflict detection. A device may comprise, for example, a memory, a processor and a fast conflict detection module (FCDM) to cause the processor to perform fast conflict detection. The FCDM may cause the processor to read a first and second vector from memory, and to then generate summaries based on the first and second vectors. The summaries may be, for example, shortened versions of write and read addresses in the first and second vectors. The FCDM may then cause the processor to distribute the summaries into first and second summary vectors, and may then determine potential conflicts between the first and second vectors by comparing the first and second summary vectors. The summaries may be distributed into the first and second summary vectors in a manner allowing all of the summaries to be compared to each other in one vector comparison transaction.

Abstract translation: 本公开涉及快速近似冲突检测。 设备可以包括例如存储器，处理器和快速冲突检测模块（FCDM），以使处理器执行快速冲突检测。 FCDM可以使处理器从存储器读取第一和第二矢量，然后基于第一和第二矢量生成汇总。 摘要可以是例如第一和第二向量中的写入和读取地址的缩写版本。 然后，FCDM可以使处理器将摘要分发到第一和第二摘要向量中，然后可以通过比较第一和第二概括向量来确定第一和第二向量之间的潜在冲突。 总结可以以允许在一个向量比较事务中将所有概要相互比较的方式分发到第一和第二摘要向量中。

公开(公告)号：US09910650B2

公开(公告)日：2018-03-06

申请号：US14497157

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Albert Hartono ,  Nalini Vasudevan ,  Sara S. Baghsorkhi ,  Cheng Wang ,  Youfeng Wu

IPC: G06F9/45 ,  G06F9/455

CPC classification number: G06F8/452 ,  G06F9/4552

Abstract: A computer-implemented method for managing loop code in a compiler includes using a conflict detection procedure that detects across-iteration dependency for arrays of single memory addresses to determine whether a potential across-iteration dependency exists for arrays of memory addresses for ranges of memory accessed by the loop code.

公开(公告)号：US20170322786A1

公开(公告)日：2017-11-09

申请号：US15660603

申请日：2017-07-26

Applicant: Intel Corporation

Inventor： Jayashankar Bharadwaj ,  Nalini Vasudevan ,  Albert Hartono ,  Sara S Baghsorkhi

IPC: G06F9/45 ,  G06F9/06 ,  G06F9/44 ,  G06F9/30

CPC classification number: G06F8/4441 ,  G06F8/443 ,  G06F8/452 ,  G06F9/06 ,  G06F9/30 ,  G06F9/44

Abstract: Methods and systems to convert a scalar computer program loop having loop-carried dependences into a vector computer program loop are disclosed. One such method includes, at runtime, identifying, by executing an instruction with one or more processors, a first loop iteration that cannot be executed in parallel with a second loop iteration due to a set of conflicting scalar loop operations. The first loop iteration is executed after the second loop iteration. The method also includes sectioning, by executing an instruction with one or more processors, a vector loop into vector partitions including a first vector partition. The first vector partition executes consecutive loop iterations in parallel and the consecutive loop iterations start at the second loop iteration and end before the first loop iteration.

公开(公告)号：US09720667B2

公开(公告)日：2017-08-01

申请号：US14222040

申请日：2014-03-21

Applicant: Intel Corporation

Inventor： Sara S. Baghsorkhi ,  Albert Hartono ,  Youfeng Wu ,  Nalini Vasudevan ,  Cheng Wang

IPC: G06F9/45

CPC classification number: G06F8/452

Abstract: Technologies for automatic loop vectorization include a computing device with an optimizing compiler. During an optimization pass, the compiler identifies a loop and generates a transactional code segment including a vectorized implementation of the loop body including one or more vector memory read instructions capable of generating an exception. The compiler also generates a non-transactional fallback code segment including a scalar implementation of the loop body that is executed in response to an exception generated within the transactional code segment. The compiler may detect whether the loop contains a memory read dependent on a condition that may be updated in a previous iteration or whether the loop contains a potential data dependence between two iterations. The compiler may generate a dynamic check for an actual data dependence and an explicit transactional abort instruction to be executed when an actual data dependence exists. Other embodiments are described and claimed.

公开(公告)号：US09710279B2

公开(公告)日：2017-07-18

申请号：US14497833

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Nalini Vasudevan ,  Cheng Wang ,  Youfeng Wu ,  Albert Hartono ,  Sara S. Baghsorkhi

IPC: G06F9/312 ,  G06F9/38 ,  G06F15/76 ,  G06F9/30 ,  G06F15/80

CPC classification number: G06F9/3842 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/3013 ,  G06F9/30174 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3838 ,  G06F15/8053

Abstract: An apparatus and method for speculative vectorization. For example, one embodiment of a processor comprises: a queue comprising a set of locations for storing addresses associated with vectorized memory access instructions; and execution logic to execute a first vectorized memory access instruction to access the queue and to compare a new address associated with the first vectorized memory access instruction with existing addresses stored within a specified range of locations within the queue to detect whether a conflict exists, the existing addresses having been previously stored responsive to one or more prior vectorized memory access instructions.

公开(公告)号：US20160092285A1

公开(公告)日：2016-03-31

申请号：US14497157

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Albert Hartono ,  Nalini Vasudevan ,  Sara S. Baghsorkhi ,  Cheng Wang ,  Youfeng Wu

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F8/452 ,  G06F9/4552

Abstract: A computer-implemented method for managing loop code in a compiler includes using a conflict detection procedure that detects across-iteration dependency for arrays of single memory addresses to determine whether a potential across-iteration dependency exists for arrays of memory addresses for ranges of memory accessed by the loop code.

Abstract translation: 用于管理编译器中的循环代码的计算机实现的方法包括使用冲突检测过程，其检测单个存储器地址的阵列的跨迭代依赖性，以确定存储器地址范围内的存储器地址的阵列是否存在潜在的跨迭代依赖性 通过循环代码。