公开(公告)号：US20170229342A1

公开(公告)日：2017-08-10

申请号：US15495137

申请日：2017-04-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  MICHAEL J. JACKSON ,  MICHAEL L. HATTENDORF ,  SUBHASH M. JOSHI

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/76834 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).