公开(公告)号：US20170229342A1

公开(公告)日：2017-08-10

申请号：US15495137

申请日：2017-04-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  MICHAEL J. JACKSON ,  MICHAEL L. HATTENDORF ,  SUBHASH M. JOSHI

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L21/76834 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/30604 ,  H01L21/76805 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76897 ,  H01L21/823418 ,  H01L29/41775 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).

公开(公告)号：US20170133376A1

公开(公告)日：2017-05-11

申请号：US15115825

申请日：2014-03-24

Applicant: Intel Corporation

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE ,  SUBHASH M. JOSHI

IPC: H01L27/092 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/3065

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/3065 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/785

Abstract: Techniques are disclosed for sculpting and cladding the channel region of fins on a semiconductor substrate during a replacement gate process (e.g., for transistor channel applications). The sculpting and cladding can be performed when the channel region of the fins are re-exposed after the dummy gate used in the replacement gate process is removed. The sculpting includes performing a trim etch on the re-exposed channel region of the fins to narrow a width of the fins (e.g., by 2-6 nm). A cladding layer, which may include germanium (Ge) or silicon germanium (SiGe), can then be deposited on the trimmed fins, leaving the source/drain regions of the fins unaffected. The sculpting and cladding may be performed in-situ or without air break to increase the quality of the trimmed fins (e.g., as compared to an ex-situ process).