公开(公告)号：US20190065281A1

公开(公告)日：2019-02-28

申请号：US15859385

申请日：2017-12-30

申请人： Intel Corporation

发明人： Francesc Guim Bernat ,  Evan Custodio ,  Susanne M. Balle ,  Ramamurthy Krithivas ,  Karthik Kumar

IPC分类号： G06F9/50 ,  H04L29/08 ,  H04L12/26

摘要： Technologies for auto-migration in accelerated architectures include multiple compute sleds, accelerator sleds, and storage sleds. Each of the compute sleds includes phase detection logic to receive an indication from an application presently executing on the compute sled that indicates a compute kernel associated with the application has been offloaded to a field-programmable gate array (FPGA) of an accelerator sled. The phase detection logic is further to monitor a plurality of hardware threads associated with the application, detect whether a phase change has been detected as a function of the monitored hardware threads, and migrate, in response to having detected the phase change, the hardware threads to another compute element having a lower-performance central processing unit (CPU) relative to the CPU the application is presently being executed on. Other embodiments are described herein.

公开(公告)号：US20180088625A1

公开(公告)日：2018-03-29

申请号：US15279535

申请日：2016-09-29

申请人： Intel Corporation

发明人： Ramamurthy Krithivas ,  Mark A. Bordogna ,  James M. Sepko

IPC分类号： G06F1/14 ,  G06F1/12

摘要： Disclosed herein are systems and methods for initializing and synchronizing a protected real time clock via hardware connections. For example, in some embodiments, a protected real time clock on a trusted execution environment may initialize via a hardware connection to a master clock, which is synchronized to a trusted time source via a hardware connection. In some embodiments, a protected real time clock on a trusted execution environment may initialize to a master clock during a system hardware reset sequence. In some embodiments, before a system is running normally, a real time clock on an integrated Intellectual Property agent may initialize and synchronize to a protected real time clock via a hardware connection. In some embodiments, after a system is running normally, a real time clock on a discrete device may initialize and synchronize to a protected real time clock via a hardware connection.

公开(公告)号：US09817787B2

公开(公告)日：2017-11-14

申请号：US14669295

申请日：2015-03-26

申请人： Intel Corporation

发明人： Mohan K. Nair ,  Brent D. Thomas ,  Ramamurthy Krithivas

IPC分类号： G06F13/14 ,  G06F13/36 ,  H05K7/10 ,  G06F13/42 ,  G06F9/44 ,  G06F13/40

CPC分类号： G06F13/4282 ,  G06F9/4411 ,  G06F13/4022 ,  G06F13/4068

摘要： In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.

公开(公告)号：US20230281113A1

公开(公告)日：2023-09-07

申请号：US18131980

申请日：2023-04-07

申请人： INTEL CORPORATION

发明人： Karthik Kumar ,  Francesc Guim Bernat ,  Ramamurthy Krithivas

IPC分类号： G06F12/02

CPC分类号： G06F12/023

摘要： Techniques for adaptive memory metadata allocation. A processor may determine a first memory region of a plurality of memory regions in a memory pool coupled to the processor via an interface. The processor may modify a metadata of the first memory region from a first configuration to a second configuration, where the first configuration is associated with a first number of error correction code (ECC) bits and the second configuration is associated with a second number of ECC bits.

公开(公告)号：US11693807B2

公开(公告)日：2023-07-04

申请号：US17207135

申请日：2021-03-19

申请人： Intel Corporation

发明人： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley A. Burres ,  Pawel Szymanski ,  Yi-Feng Liu

IPC分类号： G06F13/40 ,  G06F9/4401 ,  G06F9/445

CPC分类号： G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US20180335831A1

公开(公告)日：2018-11-22

申请号：US16052375

申请日：2018-08-01

申请人： Intel Corporation

发明人： Tessil Thomas ,  Phani Kumar Kandula ,  Ramamurthy Krithivas ,  Howard Chin ,  Ian M. Steiner ,  Vivek Garg

IPC分类号： G06F1/32 ,  G06F1/20

CPC分类号： G06F1/3296 ,  G06F1/206 ,  G06F1/32 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172

摘要： In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.

公开(公告)号：US20160283433A1

公开(公告)日：2016-09-29

申请号：US14669295

申请日：2015-03-26

申请人： Intel Corporation

发明人： Mohan K. Nair ,  Brent D. Thomas ,  Ramamurthy Krithivas

IPC分类号： G06F13/42 ,  G06F13/40 ,  G06F9/44

CPC分类号： G06F13/4282 ,  G06F9/4411 ,  G06F13/4022 ,  G06F13/4068

摘要： In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，节点包括独立执行指令的至少一个核心; 用于从所述至少一个核心接收信息并将所述信息包括在第一通信协议的第一分组中的第一主机设备; 耦合到所述第一主机设备以接收所述第一分组并且将所述第一分组提供给转换逻辑或第一接口以经由所述第一通信协议的第一互连与第一设备通信的选择逻辑; 所述转换逻辑在选择逻辑选择下接收第一分组，并将第一分组封装成第二通信协议的第二分组; 以及耦合到所述转换逻辑以接收所述第二分组并经由所述第二通信协议的第二互连将所述第二分组传送到第二设备的第二接口。 描述和要求保护其他实施例。

公开(公告)号：US20160087847A1

公开(公告)日：2016-03-24

申请号：US14494892

申请日：2014-09-24

申请人： INTEL CORPORATION

发明人： Ramamurthy Krithivas ,  Narayan Ranganathan ,  Mohan J. Kumar ,  John C. Leung

IPC分类号： H04L12/24 ,  H04L12/855 ,  H04L29/12

CPC分类号： H04L41/12 ,  H04L41/044 ,  H04L47/2466 ,  H04L61/2015 ,  H04L61/2507

摘要： Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.

摘要翻译： 允许管理控制器在数据中心环境中学习控制平面层次的机制。 数据中心配置在物理层次结构中，包括多个pod，rack，tray以及sleds和关联的switch。 配置在控制平面层级中并与物理层次结构中的交换机相关联的管理控制器被配置为将其IP地址添加到由DCHP服务器响应于对于IP地址请求的DCHP请求而产生的DHCP（动态主机控制协议）响应 由DHCP客户端启动，包括数据中心中的可管理性控制器，计算节点和存储节点。 随着DCHP响应遍历从DCHP服务器到DHCP客户端的转发路径的多个交换机中的每一个，插入与交换机相关联的可管理性控制器的IP地址。 在DHCP客户端收到后，插入的IP地址被提取并用于自动化控制平面层次结构的学习。

公开(公告)号：US12079153B2

公开(公告)日：2024-09-03

申请号：US18199042

申请日：2023-05-18

申请人： Intel Corporation

发明人： Balaji Parthasarathy ,  Ramamurthy Krithivas ,  Bradley Burres ,  Pawel Szymanski ,  Yi-Feng Liu

IPC分类号： G06F13/40 ,  G06F9/4401 ,  G06F9/445

CPC分类号： G06F13/4027 ,  G06F9/4403 ,  G06F9/4418 ,  G06F9/44505 ,  G06F13/4022

摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

公开(公告)号：US11294749B2

公开(公告)日：2022-04-05

申请号：US15859474

申请日：2017-12-30

申请人： Intel Corporation

发明人： Ramamurthy Krithivas ,  Anand K. Enamandram ,  Eswaramoorthi Nallusamy ,  Russell J. Wunderlich ,  Krishnakanth V. Sistla

IPC分类号： G06F11/07

摘要： Examples include techniques to collect crash data for a computing system following a catastrophic error. Examples include a management controller gathering error information from components of a computing system that includes a central processing unit (CPU) coupled with one or more companion dice following the catastrophic error. The management controller to gather the error information via a communication link coupled between the management controller, the CPU and the one or more companion dice.