公开(公告)号：US20210383880A1

公开(公告)日：2021-12-09

申请号：US16895890

申请日：2020-06-08

Applicant: Intel Corporation

Inventor： Pranav CHAVA ,  Aliasgar S. MADRASWALA ,  Sagar UPADHYAY ,  Bhaskar VENKATARAMAIAH

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C7/22

Abstract: For a nonvolatile (NV) storage media such as NAND (not AND) media that is written by a program and program verify operation, the system can apply a smart prologue operation. A smart prologue operation can selectively apply a standard program prologue, to compute program parameters for a target subblock. The smart prologue operation can selectively apply an accelerated program prologue, applying a previously-computed program parameter for a subsequent subblock of a same block of the NV storage media. Application of a prior program parameter can reduce the need to compute program parameters for the other subblocks.

公开(公告)号：US20210249092A1

公开(公告)日：2021-08-12

申请号：US16786948

申请日：2020-02-10

Applicant: INTEL CORPORATION

Inventor： Tarek Ahmed AMEEN BESHARI ,  Pranav CHAVA ,  Shantanu R. RAJWADE ,  Sagar UPADHYAY

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.