公开(公告)号：US20180122487A1

公开(公告)日：2018-05-03

申请号：US15715980

申请日：2017-09-26

Applicant: Intel Corporation

Inventor： Shantanu R. RAJWADE ,  Pranav KALAVADE ,  Neal R. MIELKE ,  Krishna K. PARAT ,  Shyam Sunder RAGHUNATHAN

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10

Abstract: The inhibit voltage is a voltage applied to wordlines adjacent to a program wordline having a memory cell to write during the program operation. The inhibit voltage for a program operation can be ramped up during the program pulse. Instead of applying a constant high inhibit voltage that results in the initial boosted channel potential reducing drastically due to leakage, a system can start the inhibit voltage lower and ramp the inhibit voltage up during the program pulse. The ramping up can be a continuous ramp or in finite discrete steps during the program pulse. Such ramping of inhibit voltage can provide better tradeoff between program disturb and inhibit disturb.

公开(公告)号：US20220172784A1

公开(公告)日：2022-06-02

申请号：US17107679

申请日：2020-11-30

Applicant: Intel Corporation

Inventor： Shantanu R. RAJWADE ,  Bayan NASRI ,  Tzu-Ning FANG ,  Rezaul HAQUE ,  Dhanashree R. KULKARNI ,  Narayanan RAMANAN ,  Matin AMANI ,  Ahsanur RAHMAN ,  Seong Je PARK ,  Netra MAHULI

IPC: G11C16/26 ,  G11C13/00

Abstract: A sense circuit performs a multistage boost, including a boost during precharge operation and a boost during the standard boost operation. The sense circuit includes an output transistor to drive a sense output based on current through a sense node which drives a gate of the output transistor. The sense circuit includes a precharge circuit to precharge the sense node and the gate of the output transistor and a boost circuit to boost the sense node. The boost circuit can be boosted during precharge by a first boost voltage, resulting in a lower boost applied to the sense node after precharge. The boost circuit boosts up the sense node by a second boost voltage lower than the first boost voltage. The boost circuit boosts the sense node down by the full boost voltage of the first boost voltage plus the second boost voltage after sensing.

公开(公告)号：US20190006016A1

公开(公告)日：2019-01-03

申请号：US15638260

申请日：2017-06-29

Applicant: INTEL CORPORATION

Inventor： Ali KHAKIFIROOZ ,  Pranav KALAVADE ,  Shantanu R. RAJWADE ,  Aliasgar S. MADRASWALA ,  Uday CHANDRASEKHAR ,  Purval S. SULE ,  Sagar UPADHYAY

IPC: G11C16/34 ,  G11C16/10 ,  G11C8/06 ,  G11C8/10 ,  G06F11/14

Abstract: A programming of a memory device configurable to reach a plurality of voltage levels is initiated. For each voltage level to be reached, a checkpoint is set up within a sequence of program pulses applied for the programming of the memory device, to determine whether a plurality of memory cells of the memory device have reached the voltage level. The programming of the memory device is aborted, in response to determining at the checkpoint that the plurality of memory cells have not reached the voltage level.

公开(公告)号：US20210249092A1

公开(公告)日：2021-08-12

申请号：US16786948

申请日：2020-02-10

Applicant: INTEL CORPORATION

Inventor： Tarek Ahmed AMEEN BESHARI ,  Pranav CHAVA ,  Shantanu R. RAJWADE ,  Sagar UPADHYAY

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24

Abstract: Provided are an apparatus, memory device, and method for using variable voltages to discharge electrons from a memory array during verify recovery operations. In response to verifying voltages in memory cells of the non-volatile memory array programmed during a programming pulse applying charges to the storage cells, a memory controller concurrently applies voltages on wordlines of the non-volatile memory array to clear the non-volatile memory array of electrons and applies voltages to the bitlines to perform bitline stabilization.

公开(公告)号：US20220366991A1

公开(公告)日：2022-11-17

申请号：US17321114

申请日：2021-05-14

Applicant: Intel Corporation

Inventor： Shantanu R. RAJWADE ,  Tarek Ahmed AMEEN BESHARI ,  Matin AMANI ,  Narayanan RAMANAN ,  Arun THATHACHARY

IPC: G11C16/34 ,  G06F3/06

Abstract: An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.

公开(公告)号：US20220208286A1

公开(公告)日：2022-06-30

申请号：US17134010

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Tarek Ahmed AMEEN BESHARI ,  Shantanu R. RAJWADE ,  Matin AMANI ,  Narayanan RAMANAN

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/30 ,  G11C16/10 ,  G11C16/26

Abstract: For a nonvolatile (NV) storage media such as NAND media that is written by a program and program verify operation, the system can determine an expected number of SSPC (selective slow programming convergence) cells for a page of cells for specific conditions of the page. The system can perform program verify with a first wordline (WL) select voltage for SSPC cell detection for a first write of the page to detect the expected number of SSPC cells. Based on the determined expected number of SSPC cells, the system can set a boost voltage to capture an expected number of SSPC cells during the program verify operation. The system performs program verify for subsequent writes to the page with a higher WL select voltage, to perform program verify for standard cells and then SSPC program verify with the boost voltage determined from the first write.

公开(公告)号：US20210104285A1

公开(公告)日：2021-04-08

申请号：US16591978

申请日：2019-10-03

Applicant: Intel Corporation

Inventor： Xiang YANG ,  Shantanu R. RAJWADE ,  Ali KHAKIFIROOZ ,  Tarek Ahmed AMEEN BESHARI

IPC: G11C16/34 ,  G11C16/08

Abstract: An apparatus is described. The apparatus includes a storage device controller having logic circuitry to apply a program voltage verification process for a first threshold level to a group of non volatile memory cells and correlate first program voltages for the group of non volatile memory cells determined from the process to a second threshold level to determine second program voltages for the second threshold level for the group of non volatile memory cells. The second threshold level is higher than the first threshold level.