公开(公告)号：US20220171627A1

公开(公告)日：2022-06-02

申请号：US17672253

申请日：2022-02-15

Applicant: Intel Corporation

Inventor： Dan BAUM ,  Michael ESPIG ,  James GUILFORD ,  Wajdi K. FEGHALI ,  Raanan SADE ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Bret TOLL ,  Elmoustapha OULD-AHMED-VALL ,  Mark J. CHARNEY ,  Vinodh GOPAL ,  Ronen ZOHAR ,  Alexander F. HEINECKE

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US20170147340A1

公开(公告)日：2017-05-25

申请号：US15396568

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F12/0897

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/384 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/125

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20250004772A1

公开(公告)日：2025-01-02

申请号：US18217499

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Kamlesh PILLAI ,  Vinodh GOPAL ,  Gurpreet Singh KALSI ,  Sreenivas SUBRAMONEY ,  Wajdi K. FEGHALI

IPC: G06F9/30

Abstract: Apparatus and method for a decompression hardware copy engine with efficient sequence overlapping copy. For example, one embodiment of an apparatus comprises: a plurality of processing cores, one or more of the plurality of processing cores to execute program code to produce a plurality of literals and sequences from a compressed data stream; and decompression acceleration circuitry to generate a decompressed data stream based on the plurality of literals and sequences, the decompression acceleration circuitry comprising: a sequence pre-processor circuit to process batches of sequences of the plurality of sequences and generate a plurality of copy instructions, the sequence pre-processor circuit to merge multiple copy operations corresponding to multiple sequences into a merged copy instruction; and a copy engine circuit to execute the copy instructions to produce the decompressed data stream.

公开(公告)号：US20200348937A1

公开(公告)日：2020-11-05

申请号：US16934003

申请日：2020-07-20

Applicant: Intel Corporation

Inventor： Dan BAUM ,  Michael ESPIG ,  James GUILFORD ,  Wajdi K. FEGHALI ,  Raanan SADE ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Bret TOLL ,  Elmoustapha OULD-AHMED-VALL ,  Mark J. CHARNEY ,  Vinodh GOPAL ,  Ronen ZOHAR ,  Alexander F. HEINECKE

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US20170147342A1

公开(公告)日：2017-05-25

申请号：US15396576

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  H04L9/06 ,  G06F12/0897 ,  G06F12/0875 ,  G06F12/1027 ,  G06F15/80 ,  G06F13/28

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30156 ,  G06F9/3802 ,  G06F9/384 ,  G06F9/3855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  G06F2213/0026 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/122

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20170147341A1

公开(公告)日：2017-05-25

申请号：US15396574

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F15/80 ,  H04L9/06 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/38 ,  G06F12/0897

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F2212/452 ,  G06F2212/68 ,  G06F2213/0026 ,  G09C1/00 ,  H04L9/3239 ,  H04L2209/122

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20240045690A1

公开(公告)日：2024-02-08

申请号：US18460497

申请日：2023-09-01

Applicant: Intel Corporation

Inventor： Dan BAUM ,  Michael ESPIG ,  James GUILFORD ,  Wajdi K. FEGHALI ,  Raanan SADE ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Bret TOLL ,  Elmoustapha OULD-AHMED-VALL ,  Mark J. CHARNEY ,  Vinodh GOPAL ,  Ronen ZOHAR ,  Alexander F. HEINECKE

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30178 ,  G06F9/30145 ,  G06F9/30036 ,  G06F9/3013 ,  G06F9/3802

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US20190042257A1

公开(公告)日：2019-02-07

申请号：US16144902

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Dan BAUM ,  Michael ESPIG ,  James GUILFORD ,  Wajdi K. FEGHALI ,  Raanan SADE ,  Christopher J. HUGHES ,  Robert VALENTINE ,  Bret TOLL ,  Elmoustapha OULD-AHMED-VALL ,  Mark J. CHARNEY ,  Vinodh GOPAL ,  Ronen ZOHAR ,  Alexander F. HEINECKE

IPC: G06F9/30 ,  G06F9/38

Abstract: Disclosed embodiments relate to matrix compress/decompress instructions. In one example, a processor includes fetch circuitry to fetch a compress instruction having a format with fields to specify an opcode and locations of decompressed source and compressed destination matrices, decode circuitry to decode the fetched compress instructions, and execution circuitry, responsive to the decoded compress instruction, to: generate a compressed result according to a compress algorithm by compressing the specified decompressed source matrix by either packing non-zero-valued elements together and storing the matrix position of each non-zero-valued element in a header, or using fewer bits to represent one or more elements and using the header to identify matrix elements being represented by fewer bits; and store the compressed result to the specified compressed destination matrix.

公开(公告)号：US20170147343A1

公开(公告)日：2017-05-25

申请号：US15396578

申请日：2016-12-31

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0897 ,  H04L9/06 ,  G06F12/1027 ,  G06F13/40 ,  G06F13/42 ,  G06F15/80 ,  G06F12/0875

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30098 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/384 ,  G06F9/3855 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F13/28 ,  G06F13/4068 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/452 ,  G06F2212/68 ,  G06F2213/0026 ,  G09C1/00 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/122

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

公开(公告)号：US20190332378A1

公开(公告)日：2019-10-31

申请号：US16450319

申请日：2019-06-24

Applicant: Intel Corporation

Inventor： Kirk S. YAP ,  Gilbert M. WOLRICH ,  James D. GUILFORD ,  Vinodh GOPAL ,  Erdinc OZTURK ,  Sean M. GULLEY ,  Wajdi K. FEGHALI ,  Martin G. DIXON

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/1027 ,  G06F12/0875 ,  H04L9/06 ,  G06F15/80 ,  H04L9/32 ,  G09C1/00 ,  G06F13/42 ,  G06F13/40 ,  G06F13/28 ,  G06F21/60 ,  G06F12/0897

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.