公开(公告)号：US12137169B2

公开(公告)日：2024-11-05

申请号：US17854911

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/00 ,  H04L9/06 ,  H04L9/08 ,  H04L9/30

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS verification manager logic to manage XMSS verification functions, a one-time signature and public key generator logic, a chain function logic to implement chain function algorithms, a low latency SHA3 hardware engine, and a register bank communicatively coupled to the XMSS verification manager logic. Other examples may be described.

公开(公告)号：US11909857B2

公开(公告)日：2024-02-20

申请号：US16724732

申请日：2019-12-23

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Marcio Juliato ,  Rafael Misoczki ,  Manoj Sastry ,  Liuyang Yang ,  Shabbir Ahmed ,  Christopher Gutierrez ,  Xiruo Liu

IPC: H04L9/06 ,  H04L9/32 ,  H04W4/40

CPC classification number: H04L9/0631 ,  H04L9/0637 ,  H04L9/3242 ,  H04W4/40 ,  H04L2209/26 ,  H04L2209/601

Abstract: Systems, apparatus, methods, and techniques for functional safe execution of encryption operations are provided. A fault tolerant counter and a complementary pair of encryption flows are provided. The fault tolerant counter may be based on a gray code counter and a hamming distance checker. The complementary pair of encryption flows have different implementations. The output from the complementary pair of encryption flows can be compared, and where different, errors generated.

公开(公告)号：US11750403B2

公开(公告)日：2023-09-05

申请号：US17816148

申请日：2022-07-29

Applicant: Intel Corporation

Inventor： Manoj Sastry ,  Rafael Misoczki ,  Jordan Loney ,  David M. Wheeler

IPC: G06F21/72 ,  H04L9/32

CPC classification number: H04L9/3247 ,  G06F21/72 ,  H04L9/3236

Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.

公开(公告)号：US11456877B2

公开(公告)日：2022-09-27

申请号：US16456187

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Vikram Suresh ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L29/06 ,  H04L9/32 ,  G06F21/76 ,  H04L9/08

Abstract: A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments. A method includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.

公开(公告)号：US11438172B2

公开(公告)日：2022-09-06

申请号：US16830844

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Manoj Sastry ,  Rafael Misoczki ,  Jordan Loney ,  David M. Wheeler

IPC: G06F21/72 ,  H04L9/32

Abstract: In one example an apparatus comprises a computer readable memory, a signing facility comprising a plurality of hardware security modules, and a state synchronization manager comprising processing circuitry to select, from the plurality of hardware security modules, a set of hardware security modules to be assigned to a digital signature process, the set of hardware security modules comprising at least a first hardware security module and a second hardware module, and assign a set of unique state synchronization counter sequences to the respective set of hardware security modules, the set of state synchronization counter sequences comprising at least a first state synchronization counter sequence and a second state synchronization counter sequence. Other examples may be described.

公开(公告)号：US20190319799A1

公开(公告)日：2019-10-17

申请号：US16455921

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08 ,  G06F9/38

Abstract: In one example an apparatus comprises a computer readable memory, a signature logic to generate a signature to be transmitted in association with a message, the signature logic to apply a hash-based signature scheme to the message using a private key to generate the signature comprising a public key, or a verification logic to verify a signature received in association with the message, the verification logic to apply the hash-based signature scheme to verify the signature using the public key, and an accelerator logic to apply a structured order to at least one set of inputs to the hash-based signature scheme. Other examples may be described.

公开(公告)号：US12081680B2

公开(公告)日：2024-09-03

申请号：US17492830

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Moreno Ambrosin ,  Kathiravetpillai Sivanesan ,  Rafael Misoczki ,  Sridhar Sharma ,  Ignacio Alvarez

IPC: H04L9/32 ,  H04L9/06 ,  H04L9/08

CPC classification number: H04L9/3273 ,  H04L9/0643 ,  H04L9/0866 ,  H04L9/0869 ,  H04L9/0872 ,  H04L9/0891 ,  H04L9/0894 ,  H04L9/3213 ,  H04L9/3242 ,  H04L9/3247 ,  H04L9/3297 ,  H04L2209/84

Abstract: Systems, apparatuses and methods may provide for infrastructure node technology that conducts a mutual authentication with a vehicle and verifies, if the mutual authentication is successful, location information received from the vehicle. The infrastructure node technology may also send a token to the vehicle if the location information is verified, wherein the token includes an attestation that the vehicle was present in a location associated with the location information at a specified moment in time. Additionally, vehicle technology may conduct a mutual authentication with an infrastructure node and send, if the mutual authentication is successful, location information to the infrastructure node. The vehicle technology may also receive a token from the infrastructure node.

公开(公告)号：US11770258B2

公开(公告)日：2023-09-26

申请号：US17562461

申请日：2021-12-27

Applicant: Intel Corporation

Inventor： Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Santosh Ghosh ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/08 ,  H04L9/00

CPC classification number: H04L9/3239 ,  H04L9/0869 ,  H04L9/3247 ,  H04L9/50

Abstract: In one example an apparatus comprises a computer readable memory, hash logic to generate a message hash value based on an input message, signature logic to generate a signature to be transmitted in association with the message, the signature logic to apply a hash-based signature scheme to a private key to generate the signature comprising a public key, and accelerator logic to pre-compute at least one set of inputs to the signature logic. Other examples may be described.

公开(公告)号：US20220141042A1

公开(公告)日：2022-05-05

申请号：US17492830

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Moreno Ambrosin ,  Kathiravetpillai Sivanesan ,  Rafael Misoczki ,  Sridhar Sharma ,  Ignacio Alvarez

IPC: H04L9/32 ,  H04L9/08 ,  H04L9/06

Abstract: Systems, apparatuses and methods may provide for infrastructure node technology that conducts a mutual authentication with a vehicle and verifies, if the mutual authentication is successful, location information received from the vehicle. The infrastructure node technology may also send a token to the vehicle if the location information is verified, wherein the token includes an attestation that the vehicle was present in a location associated with the location information at a specified moment in time. Additionally, vehicle technology may conduct a mutual authentication with an infrastructure node and send, if the mutual authentication is successful, location information to the infrastructure node. The vehicle technology may also receive a token from the infrastructure node.

公开(公告)号：US11303429B2

公开(公告)日：2022-04-12

申请号：US16455950

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Santosh Ghosh ,  Vikram Suresh ,  Sanu Mathew ,  Manoj Sastry ,  Andrew H. Reinders ,  Raghavan Kumar ,  Rafael Misoczki

IPC: H04L9/06 ,  G06F7/503 ,  G06F9/30 ,  H04L9/32

Abstract: In one example an apparatus comprises a computer readable memory, an XMSS operations logic to manage XMSS functions, a chain function controller to manage chain function algorithms, a secure hash algorithm-2 (SHA2) accelerator, a secure hash algorithm-3 (SHA3) accelerator, and a register bank shared between the SHA2 accelerator and the SHA3 accelerator. Other examples may be described.