-
公开(公告)号:US20180373923A1
公开(公告)日:2018-12-27
申请号:US15876846
申请日:2018-01-22
Applicant: Intel Corporation
Inventor: Ansuya Negi , Scott Pfursich , David L. Graumann , Ranjit S. Narjala , Rahuldeva Ghosh
CPC classification number: G06K9/00288 , G06K9/00228 , G06K9/00261 , G06K9/00268 , G06K9/00302 , G06K9/00604 , G06K9/00892 , G06K9/00899 , G06K9/46 , G06K9/52 , H04L63/0861 , H04W12/06
Abstract: System and techniques for spoofing detection in image biometrics are described herein. A sequence of images may be obtained from a camera; a first plurality of images in the sequence of images including a representation of a user body part, and a second plurality of images in the sequence of images including a representation of an environment of the user. A marker may be created for the representation of the body part. A feature of the environment of the user present during the second plurality of images may be identified in the sequence of images using a third group of circuits. A correlation between the marker and the feature of the environment in the sequence of images may be quantified to produce a synchronicity metric of the degree to which the marker and the feature of the environment correlate.
-
公开(公告)号:US20160335483A1
公开(公告)日:2016-11-17
申请号:US14779540
申请日:2015-03-27
Applicant: INTEL CORPORATION
Inventor: Scott Pfursich , David L. Graumann , Rahuldeva Ghosh , Ansuya Negi , Ranjit S Narjala
CPC classification number: G06K9/00288 , G06K9/00228 , G06K9/00261 , G06K9/00268 , G06K9/00302 , G06K9/00604 , G06K9/00892 , G06K9/00899 , G06K9/46 , G06K9/52 , H04L63/0861 , H04W12/06
Abstract: System and techniques for spoofing detection in image biometrics are described herein. A sequence of images may be obtained from a camera; a first plurality of images in the sequence of images including a representation of a user body part, and a second plurality of images in the sequence of images including a representation of an environment of the user. A marker may be created for the representation of the body part. A feature of the environment of the user present during the second plurality of images may be identified in the sequence of images using a third group of circuits. A correlation between the marker and the feature of the environment in the sequence of images may be quantified to produce a synchronicity metric of the degree to which the marker and the feature of the environment correlate.
Abstract translation: 本文描述了用于图像生物测定中的欺骗检测的系统和技术。 可以从相机获得图像序列; 图像序列中的第一多个图像,包括用户主体部分的表示,以及包括用户的环境的表示的图像序列中的第二多个图像。 可以为身体部位的表示创建标记。 可以使用第三组电路在图像序列中识别在第二多个图像期间存在的用户的环境的特征。 可以量化图像序列中的标记和环境特征之间的相关性,以产生标记和环境特征相关的程度的同步度量。
-
公开(公告)号:US20160142702A1
公开(公告)日:2016-05-19
申请号:US14664475
申请日:2015-03-20
Applicant: Intel Corporation
Inventor: David L. Graumann , Rahuldeva Ghosh , Scott Pfursich
Abstract: A user authentication system and method. A two-dimensional image of a scene is obtained and range information obtained from the scene is aligned with the two-dimensional image. One or more depth regions is identified and image segments corresponding to the one or more depth regions are selected within the two-dimensional image. Brightness operations are performed on one or more of the selected image segments to form a corrected image.
Abstract translation: 用户认证系统和方法。 获得场景的二维图像,并且从场景获得的范围信息与二维图像对准。 识别一个或多个深度区域,并且在二维图像内选择对应于一个或多个深度区域的图像段。 对一个或多个所选择的图像片段执行亮度操作以形成校正图像。
-
公开(公告)号:US12248570B2
公开(公告)日:2025-03-11
申请号:US17739930
申请日:2022-05-09
Applicant: Intel Corporation
Inventor: Paul Carlson , Rahuldeva Ghosh , Baiju Patel , Zhong Chen
Abstract: The present disclosure is directed to systems and methods for detecting side-channel exploit attacks such as Spectre and Meltdown. Performance monitoring circuitry includes first counter circuitry to monitor CPU cache misses and second counter circuitry to monitor DTLB load misses. Upon detecting an excessive number of cache misses and/or load misses, the performance monitoring circuitry transfers the first and second counter circuitry data to control circuitry. The control circuitry determines a CPU cache miss to DTLB load miss ratio for each of a plurality of temporal intervals. The control circuitry the identifies, determines, and/or detects a pattern or trend in the CPU cache miss to DTLB load miss ratio. Upon detecting a deviation from the identified CPU cache miss to DTLB load miss ratio pattern or trend indicative of a potential side-channel exploit attack, the control circuitry generates an output to alert a system user or system administrator.
-
公开(公告)号:US11372972B2
公开(公告)日:2022-06-28
申请号:US16233810
申请日:2018-12-27
Applicant: Intel Corporation
Inventor: Paul Carlson , Rahuldeva Ghosh , Baiju Patel , Zhong Chen
Abstract: The present disclosure is directed to systems and methods for detecting side-channel exploit attacks such as Spectre and Meltdown. Performance monitoring circuitry includes first counter circuitry to monitor CPU cache misses and second counter circuitry to monitor DTLB load misses. Upon detecting an excessive number of cache misses and/or load misses, the performance monitoring circuitry transfers the first and second counter circuitry data to control circuitry. The control circuitry determines a CPU cache miss to DTLB load miss ratio for each of a plurality of temporal intervals. The control circuitry the identifies, determines, and/or detects a pattern or trend in the CPU cache miss to DTLB load miss ratio. Upon detecting a deviation from the identified CPU cache miss to DTLB load miss ratio pattern or trend indicative of a potential side-channel exploit attack, the control circuitry generates an output to alert a system user or system administrator.
-
6.
公开(公告)号:US20220091961A1
公开(公告)日:2022-03-24
申请号:US17541246
申请日:2021-12-03
Applicant: Intel Corporation
Inventor: Zheng Zhang , Rahuldeva Ghosh
IPC: G06F11/34 , G06F11/30 , G06F9/38 , G06F9/4401
Abstract: A processor includes one or more processing cores, and a performance monitoring unit (PMU), the PMU including one or more performance monitoring counters; a PMU memory to store a PMU kernel, the PMU kernel including one or more programmable PMU functions; and a PMU processor to load the PMU kernel and concurrently execute the one or more programmable PMU functions of the PMU kernel to concurrently access the one or more performance counters.
-
公开(公告)号:US09712744B2
公开(公告)日:2017-07-18
申请号:US14779879
申请日:2014-12-19
Applicant: Intel Corporation
Inventor: Rahuldeva Ghosh , Ranjit S. Narjala , Sanjay Bakshi
CPC classification number: H04N5/23222 , G06K9/00221 , G06K9/00281 , G06K9/00912 , G06K9/036 , G06K9/2027 , G06K9/4642 , G06T5/00 , G06T7/0002 , G06T2207/20172 , G06T2207/30168
Abstract: A user authentication system and method. The user authentication system includes a camera and a processor connected to the camera. The processor receives images from the camera, searches for a user feature in the images, determines if the images require correction, adjusts camera controls in a pre-defined order to provide desired corrections, applies the desired corrections to subsequent images and authenticates the user based on the user feature in the corrected images.
-
公开(公告)号:US20160328621A1
公开(公告)日:2016-11-10
申请号:US14779842
申请日:2014-12-19
Applicant: Intel Corporation
Inventor: Ansuya Negi , David L. Graumann , Rahuldeva Ghosh , Ranjit S Narjala
IPC: G06K9/00
CPC classification number: G06K9/00899 , G06K9/00221 , G06K9/4604
Abstract: Systems and techniques for facial spoofing detection in image based biometrics are described herein. A marker may be created for a representation of a face in a first plurality of images of a sequence of images. The marker corresponds to a facial feature of the face. An environmental feature of an environment of the face may be identified across a second plurality of images of the sequence of images. A correlation between the marker and the environmental feature in the sequence of images may be quantified to produce a synchronicity metric. A spoofing attempt may be indicated in response to the synchronicity metric meeting a threshold.
Abstract translation: 本文描述了基于图像的生物识别技术中的面部欺骗检测的系统和技术。 可以为图像序列的第一多个图像中的脸部的表示创建标记。 标记对应于脸部的面部特征。 可以在图像序列的第二多个图像中识别脸部环境的环境特征。 可以对图像序列中的标记和环境特征之间的相关性进行量化以产生同步度量。 可以响应于满足阈值的同步度量来指示欺骗尝试。
-
9.
公开(公告)号:US20160140390A1
公开(公告)日:2016-05-19
申请号:US14749193
申请日:2015-06-24
Applicant: Intel Corporation
Inventor: Rahuldeva Ghosh , Ansuya Negi
CPC classification number: G06K9/00617 , G06K9/00268 , G06K9/00597 , G06K9/00604 , G06K9/00906 , G06K9/52 , G06K2009/4666 , G06T7/20 , G06T2207/30201 , H04N5/2256 , H04N5/33
Abstract: Techniques for liveness detection using progressive eyelid tracking are disclosed. A series of frames of a user are captured by a camera. The user's face, including a pair of eyes and eyelids, are detected within each of a plurality of captured frames. A respective pair of regions of interest is extracted from each captured frame within the plurality of respective captured frames, each respective region of interest including a respective eye of the respective pair of eyes detected and a respective eyelid corresponding to the respective eye. A respective score corresponding to a percentage of the respective eye unobstructed by the respective eyelid is calculated for each region of interest. A liveness indication is generated by a pattern recognizer analyzing the series of respective pairs of scores for an abnormal eyelid movement sequence.
Abstract translation: 公开了使用渐进式眼睑跟踪的活体检测技术。 用户的一系列帧由相机捕获。 在多个捕获的帧的每一个内检测用户的脸部,包括一对眼睛和眼皮。 从多个相应拍摄帧中的每个拍摄帧中提取相应的一对感兴趣区域,每个相关感兴趣区域包括检测到的各对眼睛的相应眼睛以及对应于相应眼睛的相应眼睑。 针对每个感兴趣区域计算相应于相应眼睛不被相应眼睑阻挡的百分比的相应分数。 模式识别器生成分析用于异常眼睑移动序列的各对成绩的一系列的活动指示。
-
公开(公告)号:US20220335127A1
公开(公告)日:2022-10-20
申请号:US17739930
申请日:2022-05-09
Applicant: Intel Corporation
Inventor: Paul Carlson , Rahuldeva Ghosh , Baiju Patel , Zhong Chen
Abstract: The present disclosure is directed to systems and methods for detecting side-channel exploit attacks such as Spectre and Meltdown. Performance monitoring circuitry includes first counter circuitry to monitor CPU cache misses and second counter circuitry to monitor DTLB load misses. Upon detecting an excessive number of cache misses and/or load misses, the performance monitoring circuitry transfers the first and second counter circuitry data to control circuitry. The control circuitry determines a CPU cache miss to DTLB load miss ratio for each of a plurality of temporal intervals. The control circuitry the identifies, determines, and/or detects a pattern or trend in the CPU cache miss to DTLB load miss ratio. Upon detecting a deviation from the identified CPU cache miss to DTLB load miss ratio pattern or trend indicative of a potential side-channel exploit attack, the control circuitry generates an output to alert a system user or system administrator.
-
-
-
-
-
-
-
-
-