-
公开(公告)号：US20200287133A1
公开(公告)日：2020-09-10
申请号：US16295681
申请日：2019-03-07
Applicant: INTEL CORPORATION
Inventor： Santanu Sarkar , Farrell M. Good
Abstract: A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300° C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.
-
公开(公告)号：US11527716B2
公开(公告)日：2022-12-13
申请号：US16295681
申请日：2019-03-07
Applicant: INTEL CORPORATION
Inventor： Santanu Sarkar , Farrell M. Good
Abstract: A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300° C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.
-
公开(公告)号：US20200287129A1
公开(公告)日：2020-09-10
申请号：US16295671
申请日：2019-03-07
Applicant: INTEL CORPORATION
Inventor： Santanu Sarkar , Andrea Gotti , Adam William Saxler
Abstract: A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.
-
公开(公告)号：US11538988B2
公开(公告)日：2022-12-27
申请号：US16295671
申请日：2019-03-07
Applicant: INTEL CORPORATION
Inventor： Santanu Sarkar , Andrea Gotti , Adam William Saxler
Abstract: A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.
-
-
-
Search Results
4
records
(took 0.011 seconds)
