公开(公告)号：US20200287133A1

公开(公告)日：2020-09-10

申请号：US16295681

申请日：2019-03-07

Applicant: INTEL CORPORATION

Inventor： Santanu Sarkar ,  Farrell M. Good

IPC: H01L45/00 ,  H01L27/24

Abstract: A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300° C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.

公开(公告)号：US11527716B2

公开(公告)日：2022-12-13

申请号：US16295681

申请日：2019-03-07

Applicant: INTEL CORPORATION

Inventor： Santanu Sarkar ,  Farrell M. Good

IPC: H01L45/00 ,  H01L27/24

Abstract: A new liner structure for improving memory cell design is disclosed that incorporates a boron nitride dielectric layer. An example memory device includes an array of memory cells with each of at least some of the memory cells having a stack of layers, the stack comprising at least one phase change layer. A dielectric layer is provisioned over one or more sidewalls of at least the phase change layer. The dielectric layer comprises both nitrogen and boron. The dielectric layer may be part of a liner structure that includes multiple layers, such as an alternating layer stack of boron nitride and silicon nitride. The dielectric layer can be deposited at low temperature (e.g., less than about 300° C.) while maintaining a low hydrogen content and a relatively high thermal conductivity.

公开(公告)号：US11069855B2

公开(公告)日：2021-07-20

申请号：US16459419

申请日：2019-07-01

Applicant: Intel Corporation

Inventor： Kevin L. Baker ,  Robert K. Grubbs ,  Farrell M. Good ,  Ervin T. Hill ,  Bhumika Chhabra ,  Jay S. Brown

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

Abstract: An oxidation barrier for non-volatile memory with materials sensitive to temperature and/or cross contamination (e.g., chalcogenide materials) are described The barrier can be formed, for example, around the boundaries of a non-volatile memory tile (also known as a block or sub-array). For example, a non-volatile memory device can include an oxidation barrier on a side wall of a trench between adjacent memory tiles.