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    MEMORY DEVICE WITH MULTI-LAYER LINER STRUCTURE
    1.
    发明申请
    MEMORY DEVICE WITH MULTI-LAYER LINER STRUCTURE 审中-公开

    公开(公告)号：US20200287129A1

    公开(公告)日：2020-09-10

    申请号：US16295671

    申请日：2019-03-07

    Applicant: INTEL CORPORATION

    Inventor： Santanu Sarkar ,  Andrea Gotti ,  Adam William Saxler

    IPC: H01L45/00 ,  H01L25/03 ,  H01L27/24

    Abstract: A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.

    Memory device with multi-layer liner structure
    2.
    发明授权
    Memory device with multi-layer liner structure 有权

    公开(公告)号：US11538988B2

    公开(公告)日：2022-12-27

    申请号：US16295671

    申请日：2019-03-07

    Applicant: INTEL CORPORATION

    Inventor： Santanu Sarkar ,  Andrea Gotti ,  Adam William Saxler

    IPC: H01L45/00 ,  H01L25/03 ,  H01L27/24

    Abstract: A memory cell design is disclosed. The memory cell structure includes phase change and selector layers stacked between top and bottom electrodes. An ohmic contact may be included between the phase change and selector layers. A multi-layer liner structure is provided on sidewalls of the phase change layer. In some such cases, the liner structure is above and not on sidewalls of the selector layer. The liner structure includes a first dielectric layer, and a second dielectric layer on the first dielectric layer. The liner structure includes a third dielectric layer on the second dielectric layer and that is sacrificial in nature, and may not be present in the final structure. The second dielectric layer comprises a high-k dielectric material or a metal silicate material. The second dielectric layer protects the phase change layer from lateral erosion and physical vertical etch and provides etch selectivity during the fabrication process.

    Doping of selector and storage materials of a memory cell
    7.
    发明授权
    Doping of selector and storage materials of a memory cell 有权

    公开(公告)号：US10347831B2

    公开(公告)日：2019-07-09

    申请号：US16007563

    申请日：2018-06-13

    Applicant: Intel Corporation

    Inventor： Daniel Gealy ,  Andrea Gotti ,  Dale W. Collins ,  Swapnil A. Lengade

    IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

    Abstract: Doping a storage element, a selector element, or both, of a memory cell with a dopant including one or more of aluminum (Al), zirconium (Zr), hafnium (Hf), and silicon (Si), can minimize volume or density changes in a phase change memory as well as minimize electromigration, in accordance with embodiments. In one embodiment, a memory cell includes a first electrode and a second electrode, and a storage element comprising a layer of doped phase change material between the first and second electrodes, wherein the doped phase change material includes one or more of aluminum, zirconium, hafnium, and silicon. The storage element, a selector element, or both can be doped using techniques such as cosputtering or deposition of alternating layers of a dopant layer and a storage (or selector) material.

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