公开(公告)号：US12212504B2

公开(公告)日：2025-01-28

申请号：US16260785

申请日：2019-01-29

Applicant: Intel Corporation

Inventor： Ben-Zion Friedman ,  Noam Elati ,  Sarig Livne

IPC: H04L49/253 ,  H04L41/06 ,  H04L43/16 ,  H04L49/90 ,  H04L49/901

Abstract: Techniques to use descriptors for packet transmit scheduling include grouping a plurality of data descriptors associated with blocks of data with a single descriptor. The single descriptor to include information related to the plurality of data descriptors. The single descriptor to be used to schedule transmission of the blocks of data from a computing platform.

公开(公告)号：US10812402B2

公开(公告)日：2020-10-20

申请号：US16236127

申请日：2018-12-28

Applicant: INTEL CORPORATION

Inventor： Robert Southworth ,  Ben-Zion Friedman ,  Robert Munoz ,  Sarig Livne ,  Chih-Jen Chang ,  Yue Yang ,  Partick Fleming

IPC: H04L12/841 ,  H04L12/26 ,  H04L12/927 ,  H04L12/819 ,  H04L12/815 ,  H04L12/813 ,  H04J3/06

Abstract: Apparatuses and methods for managing jitter resulting from processing through a network interface pipeline are disclosed. In embodiments, a network traffic scheduler annotates packets to be transmitted over a bandwidth-limited network connection with time relationship information to ensure downstream bandwidth limitations are not violated. Following processing through a network interface pipeline, a jitter shaper inspects the annotated time relationship information and pipeline-imposed delays and, by imposing a variable delay, reestablishes bandwidth-complaint time relationships based upon the annotated time relationship information and configured tolerances.

公开(公告)号：US20230050776A1

公开(公告)日：2023-02-16

申请号：US17957888

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Sarig Livne ,  Noam Elati ,  Yotam Nizri ,  Gregory Nizan Miron

IPC: H04L49/9047 ,  H04L47/52

Abstract: A circuitry of a network interface device of a computing network is to: access a first message from a server architecture of the computing network, the first message including a timestamp based on a time at which the circuitry is to access, from a host memory, one or more data packet descriptors that correspond to a data packet to be transmitted to the computing network from the network interface device; send, for transmission to the server architecture and at a transmission time based on the timestamp, a second message, the second message including a request to access the one or more data packet descriptors; and subsequent to sending the second message for transmission, access the one or more data packet descriptors to determine one or more addresses for the data packet in the host memory.

公开(公告)号：US10951475B2

公开(公告)日：2021-03-16

申请号：US16457100

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Sarig Livne ,  Ben-Zion Friedman ,  Noam Elati

IPC: H04L12/24 ,  G06F12/1027 ,  H04W72/12 ,  H04W88/12

Abstract: Technologies for performing dynamic configurations to a transmit scheduler of a network device with minimal downtime are disclosed. The transmit scheduler includes a topology of scheduling nodes. The transmit scheduler identifies, from a number of configuration operations to be executed on one or more of the scheduling nodes, one or more first configuration operations to be executed while the scheduling nodes are active, one or more second configuration operations to be executed while the scheduling nodes are inactive, and one or more third configuration operations to be executed via a cache. The first operations are executed as part of a background process. The second operations are executed while the scheduling nodes are inactive. The third operations are executed via the cache.

公开(公告)号：US10791057B2

公开(公告)日：2020-09-29

申请号：US16175734

申请日：2018-10-30

Applicant: Intel Corporation

Inventor： Sarig Livne ,  Ben-Zion Friedman ,  Ronen Aharon Hyatt ,  Nir Tiser ,  Robert J. Munoz

IPC: H04L12/815 ,  H04L12/741 ,  H04L12/911 ,  H04L12/927 ,  H04L12/825

Abstract: Techniques to schedule transmission of a packet from a computing platform include calculating adjustments to portions of the packet to cause corrections to at least one portion of the packet. An adjustment to a scheduled transmission of the packet is made based on the corrections.

公开(公告)号：US20190327132A1

公开(公告)日：2019-10-24

申请号：US16457100

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Sarig Livne ,  Ben-Zion Friedman ,  Noam Elati

IPC: H04L12/24 ,  H04W88/12 ,  H04W72/12 ,  G06F12/1027

Abstract: Technologies for performing dynamic configurations to a transmit scheduler of a network device with minimal downtime are disclosed. The transmit scheduler includes a topology of scheduling nodes. The transmit scheduler identifies, from a number of configuration operations to be executed on one or more of the scheduling nodes, one or more first configuration operations to be executed while the scheduling nodes are active, one or more second configuration operations to be executed while the scheduling nodes are inactive, and one or more third configuration operations to be executed via a cache. The first operations are executed as part of a background process. The second operations are executed while the scheduling nodes are inactive. The third operations are executed via the cache.