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    NETWORK LAYER 7 OFFLOAD TO INFRASTRUCTURE PROCESSING UNIT FOR SERVICE MESH
    1.
    发明申请
    NETWORK LAYER 7 OFFLOAD TO INFRASTRUCTURE PROCESSING UNIT FOR SERVICE MESH 有权

    公开(公告)号：US20220014459A1

    公开(公告)日：2022-01-13

    申请号：US17486579

    申请日：2021-09-27

    Applicant: Intel Corporation

    Inventor： Mrittika Ganguli ,  Anjali Jain ,  Reshma Lal ,  Edwin Verplanke ,  Priya Autee ,  Chih-Jen Chang ,  Abhirupa Layek ,  Nupur Jain

    IPC: H04L12/751 ,  H04L12/715 ,  G06F13/28 ,  G06F13/16

    Abstract: Examples described herein relate to network layer 7 (L7) offload to an infrastructure processing unit (IPU) for a service mesh. An apparatus described herein includes an IPU comprising an IPU memory to store a routing table for a service mesh, the routing table to map shared memory address spaces of the IPU and a host device executing one or more microservices, wherein the service mesh provides an infrastructure layer for the one or more microservices executing on the host device; and one or more IPU cores communicably coupled to the IPU memory, the one or more IPU cores to: host a network L7 proxy endpoint for the service mesh, and communicate messages between the network L7 proxy endpoint and an L7 interface device of the one or more microservices by copying data between the shared memory address spaces of the IPU and the host device based on the routing table.

    TECHNOLOGIES FOR MANAGING EXACT MATCH HASH TABLE GROWTH
    2.
    发明申请
    TECHNOLOGIES FOR MANAGING EXACT MATCH HASH TABLE GROWTH 审中-公开

    公开(公告)号：US20190044859A1

    公开(公告)日：2019-02-07

    申请号：US15859387

    申请日：2017-12-30

    Applicant: Intel Corporation

    Inventor： Naru Sundar ,  Chih-Jen Chang ,  Robert Southworth ,  Hsi-Cheng Chu

    IPC: H04L12/743 ,  G06F17/30

    Abstract: Technologies for managing exact match hash table growth include a network computing device which includes a compute engine and a network interface controller (NIC). The NIC is configured to allocate a plurality of physical bucket addresses in non-contiguous chunks of memory of the compute engine, configure a bucket threshold value as a function of a hash size of the hash table, generate a plurality of virtual bucket addresses as a function of the bucket threshold value, and map each generated virtual bucket address to an allocated physical bucket address. Other embodiments are described herein.

    TECHNOLOGIES FOR CONTROLLING JITTER AT NETWORK PACKET EGRESS
    3.
    发明申请
    TECHNOLOGIES FOR CONTROLLING JITTER AT NETWORK PACKET EGRESS 审中-公开

    公开(公告)号：US20190044867A1

    公开(公告)日：2019-02-07

    申请号：US15942023

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Chih-Jen Chang ,  Robert Southworth ,  Naru Dames Sundar ,  Yue Yang ,  Charles Michael Atkin ,  John Leshchuk

    IPC: H04L12/819 ,  H04L12/26 ,  H04L12/813

    Abstract: Technologies for controlling jitter at network packet egress at a source computing device include determining a switch time delta as a difference between a present switch time and a previously captured switch time upon receipt of a network packet scheduled for transmission to a target computing device and determining a host scheduler time delta as a difference between a host scheduler timestamp associated with the received network packet and a previously captured host scheduler timestamp. The source computing device is additionally configured to determine an amount of previously captured tokens present in a token bucket, determine whether there are a sufficient number of tokens available in the token bucket to transmit the received packet as a function of the switch time delta, the host scheduler time delta, and the amount of previously captured tokens present in the token bucket, and schedule the received network packet for transmission upon a determination that sufficient tokens in the token bucket.

    MULTIBANK CACHE WITH DYNAMIC CACHE VIRTUALIZATION
    5.
    发明申请
    MULTIBANK CACHE WITH DYNAMIC CACHE VIRTUALIZATION 审中-公开

    公开(公告)号：US20190042456A1

    公开(公告)日：2019-02-07

    申请号：US16021319

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Yakov Evgeni Ginzburg ,  Naru Dames Sundar ,  Chih-Jen Chang ,  Amir Keren ,  Ravi Tangirala

    IPC: G06F12/0893 ,  G06F12/084 ,  G06F12/1018 ,  G06F9/455

    Abstract: There is disclosed in one example a computing system, including: a processor including one or more computing cores; a cache having n discrete cache banks of the same cache level; and a cache controller including n discrete cache buses to communicatively couple the cache controller to the cache, wherein the cache buses are of width b, and a cache access controller configured to: receive an access request for an object of size s, wherein s>b; divide the object into k chunks of size b or smaller; and transfer the object to or from the cache in one or more iterations, the iterations including transferring n chunks of size b or smaller in parallel via the cache buses.

    TECHNOLOGIES FOR MANAGING NETWORK STATISTIC COUNTERS
    7.
    发明申请
    TECHNOLOGIES FOR MANAGING NETWORK STATISTIC COUNTERS 审中-公开

    公开(公告)号：US20180152366A1

    公开(公告)日：2018-05-31

    申请号：US15721817

    申请日：2017-09-30

    Applicant: Intel Corporation

    Inventor： Linden Cornett ,  Chih-Jen Chang ,  Manasi Deval ,  Parthasarathy Sarangam ,  Naru D. Sundar ,  Padma Akkiraju ,  Alexander Nguyen

    IPC: H04L12/26

    Abstract: Technologies for managing network statistic counters include a network interface controller (NIC) of a computing device configured to identify a statistic counter of and a software consumer associated with a received network packet and identify an active counter page as a function of the identified software consumer. The NIC is further configured to read a value of the statistic counter stored at a counter memory address of a corresponding counter identifier entry of the identified active counter page, increment a read value of the statistic counter, and write the incremented value of the statistic counter back to the counter memory address. Additionally, in response to detecting a notification triggering event, generating a notification message that includes a present value of the statistic counter and a present value of each of the other statistic counters of the active counter page, and transmit the generated notification message to the software consumer. Other embodiments are described herein.

    Processor related communications
    9.
    发明授权
    Processor related communications 有权

    公开(公告)号：US12160369B2

    公开(公告)日：2024-12-03

    申请号：US16276979

    申请日：2019-02-15

    Applicant: Intel Corporation

    Inventor： Chih-Jen Chang ,  Daniel Christian Biederman ,  Matthew James Webb ,  Wing Cheung ,  Jose Niell ,  Robert Hathaway

    IPC: H04L47/80 ,  H04L41/042 ,  H04L45/00 ,  H04L47/2425 ,  H04L47/2483 ,  H04L47/62

    Abstract: A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.

    Technologies for controlling jitter at network packet egress
    10.
    发明授权
    Technologies for controlling jitter at network packet egress 有权

    公开(公告)号：US11108697B2

    公开(公告)日：2021-08-31

    申请号：US15942023

    申请日：2018-03-30

    Applicant: Intel Corporation

    Inventor： Chih-Jen Chang ,  Robert Southworth ,  Naru Dames Sundar ,  Yue Yang ,  Charles Michael Atkin ,  John Leshchuk

    IPC: H04L12/26 ,  H04L12/819 ,  H04L12/813 ,  H04L12/721

    Abstract: Technologies for controlling jitter at network packet egress at a source computing device include determining a switch time delta as a difference between a present switch time and a previously captured switch time upon receipt of a network packet scheduled for transmission to a target computing device and determining a host scheduler time delta as a difference between a host scheduler timestamp associated with the received network packet and a previously captured host scheduler timestamp. The source computing device is additionally configured to determine an amount of previously captured tokens present in a token bucket, determine whether there are a sufficient number of tokens available in the token bucket to transmit the received packet as a function of the switch time delta, the host scheduler time delta, and the amount of previously captured tokens present in the token bucket, and schedule the received network packet for transmission upon a determination that sufficient tokens in the token bucket.

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