公开(公告)号：US09921966B2

公开(公告)日：2018-03-20

申请号：US14273649

申请日：2014-05-09

Applicant: INTEL CORPORATION

Inventor： Rakesh Krishnaiyer ,  Serge Preis ,  Hideki Ido ,  Anatoly Zvezdin

IPC: G06F12/08 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602 ,  G06F2212/621

Abstract: The present application is directed to employing prefetch to reduce write overhead. A device may comprise a processor and a cache memory. The processor may determine if data to be written to the cache memory comprises multiple cache lines wherein at least one of the cache lines will be fully written. If the data comprises at least one cache line to be fully written, then the processor may perform a “prefetch” wherein the processor may write dummy data to sections of the cache memory corresponding to the data to be written in full cache lines. The processor may then write actual data to the sections containing the dummy data without the processor first having to verify ownership of the sections. Any remaining data that will not be written in full cache lines may then be written to the cache memory utilizing a standard write transaction.