公开(公告)号：US09269436B2

公开(公告)日：2016-02-23

申请号：US14133011

申请日：2013-12-18

Applicant: Intel Corporation

Inventor： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

IPC: G11C7/02 ,  G11C11/406 ,  G06F12/10 ,  G11C14/00

CPC classification number: G11C14/0009 ,  G06F12/10 ,  G06F2212/1032 ,  G11C7/02 ,  G11C11/406

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

Abstract translation: 公开了用于基于侵入者行的逻辑地址和与易失性存储器相关联的地址转换方案来确定易失性存储器的一个或多个受害行的逻辑地址的示例。 其他的例子被描述和要求保护。

公开(公告)号：US09824754B2

公开(公告)日：2017-11-21

申请号：US15000643

申请日：2016-01-19

Applicant: INTEL CORPORATION

Inventor： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

IPC: G11C7/02 ,  G11C11/406 ,  G06F12/10 ,  G11C14/00

CPC classification number: G11C14/0009 ,  G06F12/10 ,  G06F2212/1032 ,  G11C7/02 ,  G11C11/406

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.