公开(公告)号：US10268542B2

公开(公告)日：2019-04-23

申请号：US15443707

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Matthew Goldman ,  Wayne D. Tran ,  Aliasgar S. Madraswala ,  Sungho Park

IPC: G06F11/00 ,  G06F11/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C29/04

Abstract: An apparatus comprises a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

公开(公告)号：US10268578B1

公开(公告)日：2019-04-23

申请号：US15721237

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Shankar Natarajan ,  Aliasgar S. Madraswala ,  Wayne D. Tran

IPC: G06F3/06 ,  G06F12/0804

Abstract: In one embodiment, a nonvolatile memory of a component such as a storage drive preserves write data in the event of a write data programming failure in the memory. Write data is preserved in the event of cached writes by data preservation logic in registers and data recovery logic recovers the preserved data and outputs the recovered data from the storage drive. Other aspects are described herein.