公开(公告)号：US11783893B2

公开(公告)日：2023-10-10

申请号：US17133459

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Shankar Natarajan ,  Suresh Nagarajan ,  Aliasgar S. Madraswala ,  Yihua Zhang

IPC: G11C7/10 ,  G11C11/56 ,  G11C29/42

CPC classification number: G11C11/5628 ,  G11C7/1039 ,  G11C11/5642 ,  G11C29/42

Abstract: Programming a multilevel cell (MLC) nonvolatile (NV) media can be performed with internal buffer reuse to reduce the need for external buffering. The internal buffer is on the same die as the NV media to be programmed, along with a volatile memory to store data to program. The internal buffer is to read and program data for the NV media. Programming of the NV media includes staging first partial pages in the buffer for program, reading second partial pages from the NV media to the volatile memory, storing second partial pages in the buffer, and programming the NV media with the first partial pages and the second partial pages.

公开(公告)号：US20190304543A1

公开(公告)日：2019-10-03

申请号：US16291142

申请日：2019-03-04

Applicant: Intel Corporation

Inventor： Purval Shyam Sule ,  Aliasgar S. Madraswala ,  Shantanu R. Rajwade ,  Trupti Ramkrishna Bemalkhedkar ,  Leonard Aaron Turcios ,  Kristopher H. Gaewsky

IPC: G11C16/12 ,  G11C16/10 ,  G11C11/56

Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.

公开(公告)号：US10224107B1

公开(公告)日：2019-03-05

申请号：US15720984

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Purval Shyam Sule ,  Aliasgar S. Madraswala ,  Shantanu R. Rajwade ,  Trupti Ramkrishna Bemalkhedkar ,  Leonard Aaron Turcios ,  Kristopher H. Gaewsky

IPC: G11C16/06 ,  G11C16/12 ,  G11C16/34 ,  G11C16/04

Abstract: In one embodiment, an apparatus comprises a memory comprising a first group of memory cells, a second group of memory cells, and a controller to program one or more lower pages of data to the first group of memory cells; store dynamic start voltage information, the dynamic start voltage information indicative of a rate of programming of at least a portion of the first group of memory cells; determine a start program voltage based on the dynamic start voltage information; and apply the start program voltage to the second group of memory cells during a first program pass of a program operation, the program operation to program one or more lower pages of data to the second group of memory cells.

公开(公告)号：US10109361B1

公开(公告)日：2018-10-23

申请号：US15637481

申请日：2017-06-29

Applicant: Intel Corporation

Inventor： Ali Khakifirooz ,  Pranav Kalavade ,  Rohit S. Shenoy ,  Aliasgar S. Madraswala ,  Donia Sebastian ,  Xin Guo

IPC: G11C16/04 ,  G11C16/34

Abstract: A memory programmer apparatus may include a first-level programmer to program a first-level cell portion of a multi-level memory in a first pass, a coarse programmer to coarse program a second-level cell portion of the multi-level memory in the first pass, wherein the second-level cell portion includes more levels than the first-level cell portion, and a fine programmer to fine program the second-level cell portion of the multi-level memory in a second pass from data programmed in the first-level cell portion in the first pass.

公开(公告)号：US10055137B2

公开(公告)日：2018-08-21

申请号：US15197617

申请日：2016-06-29

Applicant: INTEL CORPORATION

Inventor： Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  David B. Carlton ,  Xin Guo ,  Ryan J. Norton

IPC: G06F12/02 ,  G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688

Abstract: A first type of command is suspended, by a controller of a non-volatile memory device, in response to determining that a second type of command is waiting for execution. The first type of command is split into a plurality of chunks based on a computed criteria. A second type of command is executed in between execution of at least two chunks of the first type of command.

公开(公告)号：US11061762B2

公开(公告)日：2021-07-13

申请号：US16267323

申请日：2019-02-04

Applicant: Intel Corporation

Inventor： Naveen Prabhu Vittal Prabhu ,  Bharat M. Pathak ,  Aliasgar S. Madraswala ,  Yogesh B. Wakchaure ,  Violante Moschiano ,  Walter Di Francesco ,  Michele Incarnati ,  Antonino Giuseppe La Spina

IPC: G11C29/00 ,  G06F11/10 ,  G11C29/44 ,  G11C29/52 ,  G11C11/56 ,  G06F11/07 ,  G11C16/10 ,  G11C29/04

Abstract: A memory device that has been programmed to store a single bit or multiple bits can perform a determination of a number of threshold voltages in one or more threshold voltage level regions. Based on the number of threshold voltages meeting or exceeding a threshold level, a page of bits can be read and if the bit error rate of the page of bits is below a threshold rate, the page of bits can be stored in the cells together with other bits stored in the cells and a provided additional page of bits. However, if the bit error rate of the page of bits is at or above the threshold rate, then the bit or bits stored in the cells can be error corrected and stored together with a provided additional page of bits.

公开(公告)号：US10446238B2

公开(公告)日：2019-10-15

申请号：US15717835

申请日：2017-09-27

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Xin Guo ,  David B. Carlton ,  Purval S. Sule

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10

Abstract: Embodiments include apparatuses, methods, and computer devices including a multi-level NAND memory array and a memory controller coupled to the multi-level NAND memory array. The multi-level NAND memory array may include a first word line and a second word line. The memory controller may receive a first page of data and a second page of data together with a program command to program the first page of data and the second page of data into the multi-level NAND memory array. The memory controller may program the first page of data into a page of the first word line via a first pass, and further program the second page of data into a page of the second word line via a second pass, subsequent to the first pass. Other embodiments may also be described and claimed.

公开(公告)号：US10268542B2

公开(公告)日：2019-04-23

申请号：US15443707

申请日：2017-02-27

Applicant: INTEL CORPORATION

Inventor： Matthew Goldman ,  Wayne D. Tran ,  Aliasgar S. Madraswala ,  Sungho Park

IPC: G06F11/00 ,  G06F11/10 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C29/04

Abstract: An apparatus comprises a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits.

公开(公告)号：US12211563B2

公开(公告)日：2025-01-28

申请号：US17411919

申请日：2021-08-25

Applicant: Intel Corporation

Inventor： Sagar Upadhyay ,  Archana Tankasala ,  Aliasgar S. Madraswala ,  Shantanu Rajwade

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

Abstract: Systems, apparatuses and methods may provide for technology that conducts a pulse-verify loop sequence from a first program level in targeted NAND memory cells to a next-to-last program level in the memory cells, wherein the pulse-verify loop sequence includes an issuance of a program pulse and one or more verify pulses to the memory cells on a per program level basis, and wherein successive program pulses differ from one another by a gate step voltage amount. The technology may also issue a last level program pulse to the memory cells at a last program level, issue a single verify pulse to the memory cells after the last level program pulse, and issue a gate step pulse to the memory cells at a variable program level, wherein the variable program level differs from the last program level by an amount that is greater than the gate step voltage amount.

公开(公告)号：US11693582B2

公开(公告)日：2023-07-04

申请号：US16947592

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Aliasgar S. Madraswala ,  Ali Khakifirooz ,  Camila Jaramillo ,  John Egler ,  Netra Mahuli ,  Renjie Chen ,  Yogesh Wakchaure

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26

Abstract: An apparatus comprises a plurality of memory cells; a plurality of sense circuits, a sense circuit comprising a sense node selectively coupled to a bitline coupled to a first cell of the plurality of memory cells; and a controller to transpose a value indicative of a voltage of the first cell to the sense node; isolate the sense node from the bitline; and calibrate a parameter for the sense circuit based on outputs of the sense circuit for each of a plurality of different applied values of the parameter.