公开(公告)号：US09842015B2

公开(公告)日：2017-12-12

申请号：US14040092

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Ashok Raj ,  Mohan J. Kumar ,  Jose A. Vargas ,  William G. Auld ,  Cameron B. McNairy ,  Theodros Yigzaw ,  James B. Crossland ,  Anthony E. Luck

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0712 ,  G06F11/0724 ,  G06F11/0784 ,  G06F11/0793

Abstract: A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.

公开(公告)号：US09384076B2

公开(公告)日：2016-07-05

申请号：US14141886

申请日：2013-12-27

Applicant: Intel Corporation

Inventor： William G. Auld ,  Ashok Raj ,  Malini K. Bhandaru

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0721 ,  G06F11/0793

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for allocating machine check architecture banks. The processing device includes a plurality of machine check architecture banks to communicate a machine check error. The processing also includes an allocator to allocate during runtime of the processor a target machine check architecture bank of the plurality of machine check architecture banks. The runtime of the processor is during an occurrence of the machine check error.

Abstract translation: 根据本文公开的实施例，提供了用于分配机器检查体系结构库的系统和方法。 处理装置包括多个机器检查体系结构库，用于传送机器检查错误。 处理还包括分配器，用于在处理器的运行时间期间分配多个机器检查体系结构库中的目标机器检查体系结构库。 处理器的运行时间是在机器检查错误发生期间。