公开(公告)号：US20180095793A1

公开(公告)日：2018-04-05

申请号：US15282715

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Vikas Shivappa ,  Fenghua Yu ,  Anthony E. Luck ,  Ravi V. Shankar

IPC: G06F9/50

CPC classification number: G06F9/50 ,  G06F9/5022 ,  G06F9/5027

Abstract: Methods and apparatus to schedule operations in computing systems are disclosed. An example method includes determining, by executing an instruction with a processor, that an operation identifier is inactive, the operation identifier assigned to a first operation, the operation identifier utilized by the processor to allocate computing resources of a computing system to the first active operation and in response to a request for assignment of an operation identifier to a second operation: freeing, by executing an instruction with a processor, the operation identifier from the first operation, and assigning, by executing an instruction with a processor, the operation identifier to the second operation.

公开(公告)号：US09842015B2

公开(公告)日：2017-12-12

申请号：US14040092

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Ashok Raj ,  Mohan J. Kumar ,  Jose A. Vargas ,  William G. Auld ,  Cameron B. McNairy ,  Theodros Yigzaw ,  James B. Crossland ,  Anthony E. Luck

IPC: G06F11/00 ,  G06F11/07

CPC classification number: G06F11/0772 ,  G06F11/0712 ,  G06F11/0724 ,  G06F11/0784 ,  G06F11/0793

Abstract: A processor includes a logic to determine an error condition reported in an error bank. The error bank is communicatively coupled to the processor and is associated with logical processors of the processor. The processor includes another logic to generate an interrupt indicating the error condition. The processor includes yet another logic to selectively send the interrupt to a single one of the logical processors associated with the error bank.

公开(公告)号：US10304556B2

公开(公告)日：2019-05-28

申请号：US15395590

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Anthony E. Luck

IPC: G06F3/06 ,  G11C29/36 ,  G11C29/38 ,  G11C29/44 ,  G11C29/52 ,  G11C29/00

Abstract: An example system that includes a processor, a memory controller, a memory, and a memory device. The memory controller coupled to the processor. The memory coupled to the memory controller, the memory to store a first copy of data stored according to a first test data pattern for use by a memory scrubbing operation. The memory device coupled to the memory controller. The memory controller may mirror a first set of data stored in a first block of memory of the memory device to a second block of memory of the memory device. The memory controller may also write the first copy of data to the first block of memory as a second copy of data. The memory controller send a first message to the processor indicating a memory fault error for the first block of memory.