-
公开(公告)号:US10025535B2
公开(公告)日:2018-07-17
申请号:US14671663
申请日:2015-03-27
Applicant: Intel Corporation
Inventor: Robert E. Frickey, III , Ye Zhang
Abstract: Provided are a method, apparatus, and a system for measuring latency of a storage device. The storage device measures one or more latencies of one or more input/output (I/O) operations received from a host. The storage device transmits information on the one or more latencies to the host.
-
公开(公告)号:US10956081B2
公开(公告)日:2021-03-23
申请号:US16388761
申请日:2019-04-18
Applicant: INTEL CORPORATION
Inventor: David J. Pelster , David B. Carlton , Mark Anthony Golez , Xin Guo , Aliasgar S. Madraswala , Sagar S. Sidhpura , Sagar Upadhyay , Neelesh Vemula , Yogesh B. Wakchaure , Ye Zhang
IPC: G06F3/06
Abstract: A data structure is maintained for performing a program operation that is allowed to be suspended to perform reads in a NAND device, where the data structure indicates a plurality of tiers, where each tier of the plurality of tiers has a number of allowed suspends of the program operation while executing in the tier, and where a sum of the number of allowed suspends for all tiers of the plurality of tiers equals a maximum allowed number of suspends of the program operation. In response to performing a resume of the program operation, after performing a read following a suspend of the program operation, a determination is made of a tier of the plurality of tiers for the program operation and a subsequent suspend of the program operation is performed only after a measure of progress of the program operation has been exceeded in the determined tier.
-
公开(公告)号:US20220004335A1
公开(公告)日:2022-01-06
申请号:US17481786
申请日:2021-09-22
Applicant: Intel Corporation
Inventor: Mohammad Nasim Imtiaz Khan , Yogesh B. Wakchaure , Eric Hoffman , Neal Mielke , Shirish Bahirat , Cole Uhlman , Ye Zhang , Anand Ramalingam
IPC: G06F3/06
Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units and, in response to a read request, increment one or more global RD counters that correspond to the read request, determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit and, if so determined, increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit. Other embodiments are disclosed and claimed.
-
-