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    READ DISTURB TRACKING BASED ON STATISTICAL PROBABILITY
    1.
    发明申请
    READ DISTURB TRACKING BASED ON STATISTICAL PROBABILITY 有权

    公开(公告)号：US20220004335A1

    公开(公告)日：2022-01-06

    申请号：US17481786

    申请日：2021-09-22

    Applicant: Intel Corporation

    Inventor： Mohammad Nasim Imtiaz Khan ,  Yogesh B. Wakchaure ,  Eric Hoffman ,  Neal Mielke ,  Shirish Bahirat ,  Cole Uhlman ,  Ye Zhang ,  Anand Ramalingam

    IPC: G06F3/06

    Abstract: An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units and, in response to a read request, increment one or more global RD counters that correspond to the read request, determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit and, if so determined, increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit. Other embodiments are disclosed and claimed.

    SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT
    2.
    发明申请
    SOFT READ OPERATIONS WITH PROGRESSIVE DATA OUTPUT 有权

    公开(公告)号：US20210294698A1

    公开(公告)日：2021-09-23

    申请号：US17342993

    申请日：2021-06-09

    Applicant: Intel Corporation

    Inventor： Ali Khakifirooz ,  George Kalwitz ,  Anand Ramalingam ,  Ravi Motwani ,  Renjie Chen

    IPC: G06F11/10 ,  H03M13/45 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

    Abstract: Systems, apparatuses and methods may provide for memory controller technology including first logic to trigger, via an initial request, a hard-read and a soft-read, wherein the hard-read is to generate hard-bit information and the soft-read is to generate first soft-bit information and second soft-bit information, conduct a first error correction on the hard-bit information, and issue a subsequent request for at least the second soft-bit information if the first error correction is unsuccessful. Additionally, memory device technology may include a plurality of memory cells and second logic to conduct the hard-read and the soft-read from a memory cell in the plurality of memory cells in response to the initial request, send the hard-bit information to the controller, and withhold at least the second soft-bit information from the controller until the subsequent request is received.

    MANAGING QUALITY OF SERVICE BY ALLOCATING DIE PARALLELISM WITH VARIABLE QUEUE DEPTH
    4.
    发明申请
    MANAGING QUALITY OF SERVICE BY ALLOCATING DIE PARALLELISM WITH VARIABLE QUEUE DEPTH 有权

    公开(公告)号：US20210392083A1

    公开(公告)日：2021-12-16

    申请号：US17355915

    申请日：2021-06-23

    Applicant: Intel Corporation

    Inventor： Shirish Bahirat ,  Anand Ramalingam ,  Solomon Sagar Albert Jayaraj ,  Fnu Sachin ,  Xin Guo

    IPC: H04L12/851

    Abstract: Systems, apparatuses and methods provide for a memory controller to manage quality of service enforcement. For example, a memory controller includes logic to determine a plurality of projected bandwidth levels and a plurality of projected quality of service levels on a user-by-user basis. The projected bandwidth levels and the projected quality of service levels are determined for a plurality of device configurations based on one or more storage device parameters. A requested bandwidth level and a requested quality of service level is received from a host in response to the plurality of projected bandwidth levels and the plurality of projected quality of service levels.

    RESOURCE MANAGEMENT CONTROLLER
    7.
    发明申请
    RESOURCE MANAGEMENT CONTROLLER 有权

    公开(公告)号：US20220012094A1

    公开(公告)日：2022-01-13

    申请号：US17481940

    申请日：2021-09-22

    Applicant: Intel Corporation

    Inventor： Shirish Bahirat ,  Anand Ramalingam ,  Anjaneya Chagam Reddy

    IPC: G06F9/50 ,  G06F9/54

    Abstract: An embodiment of an electronic apparatus may comprise one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to read utilization-related information for a resource from a memory shared with a processor in response to a request from the processor for the resource, and schedule utilization of the resource based at least in part on the utilization-related information for the resource. Other embodiments are disclosed and claimed.

    Technology to manage capacity loss in storage drives
    8.
    发明授权
    Technology to manage capacity loss in storage drives 有权

    公开(公告)号：US11068175B2

    公开(公告)日：2021-07-20

    申请号：US16229679

    申请日：2018-12-21

    Applicant: Intel Corporation

    Inventor： Marcin Pioch ,  Michael Mesnier ,  Anand Ramalingam ,  Benjamin Boyer ,  Kapil Karkra ,  Piotr Wysocki

    IPC: G06F3/06 ,  G06F12/1009

    Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.

    TECHNOLOGY TO MANAGE CAPACITY LOSS IN STORAGE DRIVES
    9.
    发明申请
    TECHNOLOGY TO MANAGE CAPACITY LOSS IN STORAGE DRIVES 审中-公开

    公开(公告)号：US20190146698A1

    公开(公告)日：2019-05-16

    申请号：US16229679

    申请日：2018-12-21

    Applicant: Intel Corporation

    Inventor： Marcin Pioch ,  Michael Mesnier ,  Anand Ramalingam ,  Benjamin Boyer ,  Kapil Karkra ,  Piotr Wysocki

    IPC: G06F3/06 ,  G06F12/1009

    Abstract: A system including a storage drive and a semiconductor apparatus coupled to the storage drive, is provided. The semiconductor apparatus may include one or more substrates and logic coupled to the one or more substrates, the logic coupled to the one or more substrates to: initiate managing resources of the storage drive and, if the storage drive loses capacity, determine an amount of capacity loss, create a reserved file that is associated with logical memory space in a file system, based on the amount of the capacity loss, and erase at least a portion of the reserved file so that logical memory space associated with an un-erased portion of the reserved file is usable by the storage drive.

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