公开(公告)号：US20190296214A1

公开(公告)日：2019-09-26

申请号：US16301498

申请日：2016-06-13

Applicant: INTEL CORPORATION

Inventor： Zachary R. YOSCOVITS ,  David J. MICHALAK ,  Jeanette M. ROBERTS ,  Ravi PILLARISETTY ,  James S. CLARKE

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/02 ,  H01L39/22

Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.