公开(公告)号：US20160190060A1

公开(公告)日：2016-06-30

申请号：US14909736

申请日：2013-09-27

Applicant: Rami HOURANI ,  INTEL CORPORATION

Inventor： Robert L. Bristol ,  James M. BLACKWELL ,  Scott B. CLENDENNING ,  Florian GSTREIN ,  Eungnak HAN ,  Grant M. KLOSTER ,  Jeanette M. ROBERTS ,  Patricio E. ROMERO ,  Rami HOURANI

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/768 ,  H01L21/3205 ,  H01L23/522 ,  H01L21/3105

CPC classification number: H01L23/528 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/311 ,  H01L21/32 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract translation: 一个方面的方法包括通过通过选择性化学反应分别形成第一多个较薄层中的每一个，在具有第一表面材料的第一区域上形成第一材料的第一较厚层。 该方法还包括限制在与第一区域相邻的第二区域上的第一多个较薄层中的每一个的侵入。 在第二区域上形成第二较厚的第二材料层，其具有不同于第一表面材料的第二表面材料。

公开(公告)号：US20190296214A1

公开(公告)日：2019-09-26

申请号：US16301498

申请日：2016-06-13

Applicant: INTEL CORPORATION

Inventor： Zachary R. YOSCOVITS ,  David J. MICHALAK ,  Jeanette M. ROBERTS ,  Ravi PILLARISETTY ,  James S. CLARKE

IPC: H01L39/24 ,  H01L27/18 ,  H01L39/02 ,  H01L39/22

Abstract: Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.