PERFORMANCE MONITORING UNIT OF A PROCESSOR DETERRING TAMPERING OF COUNTER CONFIGURATION AND ENABLING VERIFIABLE DATA SAMPLING

    公开(公告)号:US20220092174A1

    公开(公告)日:2022-03-24

    申请号:US17539698

    申请日:2021-12-01

    Abstract: A secure performance monitoring unit of a processor includes one or more performance monitoring counters and a secure group manager. The secure group manager is configured to receive a request to create a secure counter group from a software (SW) process being executed by a processor, the request including identification of the one or more counters; determine availability of the one or more counters, creating the secure counter group, assign the one or more counters to the secure counter group, and save a public key of the SW process, when the one or more counters are available; receive and save a private key for the secure counter group; receive a request to configure the secure counter group from the SW process; verify the configuration using the public key of the SW process; and begin sampling of the one or more counters when the configuration is verified.

    Checkpointing for DRAM-less SSD
    8.
    发明授权

    公开(公告)号:US10754785B2

    公开(公告)日:2020-08-25

    申请号:US16021469

    申请日:2018-06-28

    Abstract: Methods and apparatus related to checkpointing for Solid State Drives (SSDs) that include no DRAM (Dynamic Random Access Memory) are described. In one embodiment, Non-Volatile Memory (NVM) stores an original Logical address to Physical address (L2P) table entry and a shadow L2P table entry. Allocation logic circuitry causes storage of the original L2P table entry and the shadow L2P table entry sequentially in the NVM. Data read from the shadow L2P table entry is capable to indicate a state of the original L2P table entry. Other embodiments are also disclosed and claimed.

    CHECKPOINTING FOR DRAM-LESS SSD
    9.
    发明申请

    公开(公告)号:US20190042462A1

    公开(公告)日:2019-02-07

    申请号:US16021469

    申请日:2018-06-28

    Abstract: Methods and apparatus related to checkpointing for Solid State Drives (SSDs) that include no DRAM (Dynamic Random Access Memory) are described. In one embodiment, Non-Volatile Memory (NVM) stores an original Logical address to Physical address (L2P) table entry and a shadow L2P table entry. Allocation logic circuitry causes storage of the original L2P table entry and the shadow L2P table entry sequentially in the NVM. Data read from the shadow L2P table entry is capable to indicate a state of the original L2P table entry. Other embodiments are also disclosed and claimed.

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