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    Data distribution in an array of neural network cores
    5.
    发明授权
    Data distribution in an array of neural network cores 有权

    公开(公告)号：US11238347B2

    公开(公告)日：2022-02-01

    申请号：US16146632

    申请日：2018-09-28

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Brian Taba ,  Andrew S. Cassidy ,  Myron D. Flickner ,  Pallab Datta ,  Hartmut Penner ,  Rathinakumar Appuswamy ,  Jun Sawada ,  John V. Arthur ,  Dharmendra S. Modha ,  Steven K. Esser ,  Jennifer Klamo

    IPC: G06N3/08 ,  G06F17/16 ,  G06N3/06 ,  G06N3/04

    Abstract: Parallel processing among arrays of physical neural cores is provided. An array of neural cores is adapted to compute, in parallel, an output activation tensor of a neural network layer. A network is operatively connected to each of the neural cores. The output activation tensor is distributed across the neural cores. An input activation tensor is distributed across the neural cores. A weight tensor is distributed across the neural cores. Each neural core's computation comprises multiplying elements of a portion of the input activation tensor at that core with elements of a portion of the weight tensor at that core, and storing the summed products in a partial sum corresponding to an element of the output activation tensor. Each element of the output activation tensor is computed by accumulating all of the partial sums corresponding to that element via the network. The partial sums for each element of the output activation tensor are computed in a sequence of steps whose order is described by tracing a path through the weight tensor that visits every weight tensor element that contributes to any partial sum.

    NEURAL NETWORK WEIGHT DISTRIBUTION FROM A GRID OF MEMORY ELEMENTS
    6.
    发明申请
    NEURAL NETWORK WEIGHT DISTRIBUTION FROM A GRID OF MEMORY ELEMENTS 有权

    公开(公告)号：US20210312305A1

    公开(公告)日：2021-10-07

    申请号：US16842035

    申请日：2020-04-07

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Jun Sawada ,  Dharmendra S. Modha ,  Andrew S. Cassidy ,  John V. Arthur ,  Tapan K. Nayak ,  Carlos O. Otero ,  Brian Taba ,  Filipp A. Akopyan ,  Pallab Datta

    IPC: G06N5/04 ,  G06N3/063

    Abstract: Neural inference chips for computing neural activations are provided. In various embodiments, a neural inference chip comprises at least one neural core, a memory array, an instruction buffer, and an instruction memory. The instruction buffer has a position corresponding to each of a plurality of elements of the memory array. The instruction memory provides at least one instruction to the instruction buffer. The instruction buffer advances the at least one instruction between positions in the instruction buffer. The instruction buffer provides the at least one instruction to at least one of the plurality of elements of the memory array from its associated position in the instruction buffer when the memory of the at least one of the plurality of elements contains data associated with the at least one instruction. Each element of the memory array provides a data block from its memory to its horizontal buffer in response to the arrival of an associated instruction from the instruction buffer. The horizontal buffer of each element of the memory array provides a data block to the horizontal buffer of another of the elements of the memory array or to the at least one neural core.

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