公开(公告)号：US12182687B2

公开(公告)日：2024-12-31

申请号：US16157852

申请日：2018-10-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John V. Arthur ,  Andrew S. Cassidy ,  Myron D. Flickner ,  Pallab Datta ,  Hartmut Penner ,  Rathinakumar Appuswamy ,  Jun Sawada ,  Dharmendra S. Modha ,  Steven K. Esser ,  Brian Taba ,  Jennifer Klamo

IPC: G06N3/063 ,  G06N3/04

Abstract: Systems for neural network computation are provided. A neural network processor comprises a plurality of neural cores. The neural network processor has one or more processor precisions per activation. The processor is configured to accept data having a processor feature dimension. A transformation circuit is coupled to the neural network processor, and is adapted to: receive an input data tensor having an input precision per channel at one or more features; transform the input data tensor from the input precision to the processor precision; divide the input data into a plurality of blocks, each block conforming to one of the processor feature dimensions; provide each of the plurality of blocks to one of the plurality of neural cores. The neural network processor is adapted to compute, by the plurality of neural cores, output of one or more neural network layers.

公开(公告)号：US12056598B2

公开(公告)日：2024-08-06

申请号：US18046301

申请日：2022-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andrew S. Cassidy ,  Rathinakumar Appuswamy ,  John V. Arthur ,  Pallab Datta ,  Steven K. Esser ,  Myron D. Flickner ,  Jennifer Klamo ,  Dharmendra S. Modha ,  Hartmut Penner ,  Jun Sawada ,  Brian Taba

IPC: G06N3/063 ,  G06N3/048 ,  G06N3/08 ,  G06N5/04 ,  G11C11/54

CPC classification number: G06N3/063 ,  G06N3/048 ,  G06N3/08 ,  G06N5/04 ,  G11C11/54

Abstract: Hardware neural network processors, are provided. A neural core includes a weight memory, an activation memory, a vector-matrix multiplier, and a vector processor. The vector-matrix multiplier is adapted to receive a weight matrix from the weight memory, receive an activation vector from the activation memory, and compute a vector-matrix multiplication of the weight matrix and the activation vector. The vector processor is adapted to receive one or more input vector from one or more vector source and perform one or more vector functions on the one or more input vector to yield an output vector. In some embodiments a programmable controller is adapted to configure and operate the neural core.

公开(公告)号：US20210264279A1

公开(公告)日：2021-08-26

申请号：US16796397

申请日：2020-02-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Steve Esser ,  Jeffrey L. McKinstry ,  Deepika Bablani ,  Rathinakumar Appuswamy ,  Dharmendra S. Modha

IPC: G06N3/08 ,  G06F17/16 ,  G06N3/04

Abstract: Learned step size quantization in artificial neural network is provided. In various embodiments, a system comprises an artificial neural network and a computing node. The artificial neural network comprises: a quantizer having a configurable step size, the quantizer adapted to receive a plurality of input values and quantize the plurality of input values according to the configurable step size to produce a plurality of quantized input values, at least one matrix multiplier configured to receive the plurality of quantized input values from the quantizer and to apply a plurality of weights to the quantized input values to determine a plurality of output values having a first precision, and a multiplier configured to scale the output values to a second precision. The computing node is operatively coupled to the artificial neural network and is configured to: provide training input data to the artificial neural network, and optimize the configurable step size based on a gradient through the quantizer and the training input data.

公开(公告)号：US10832121B2

公开(公告)日：2020-11-10

申请号：US16391092

申请日：2019-04-22

Applicant: International Business Machines Corporation

Inventor： Rathinakumar Appuswamy ,  Myron D. Flickner ,  Dharmendra S. Modha

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063 ,  G06F17/16

Abstract: Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.

公开(公告)号：US20200042856A1

公开(公告)日：2020-02-06

申请号：US16051034

申请日：2018-07-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pallab Datta ,  Andrew S. Cassidy ,  Myron D. Flickner ,  Hartmut Penner ,  Rathinakumar Appuswamy ,  Jun Sawada ,  John V. Arthur ,  Dharmendra S. Modha ,  Steven K. Esser ,  Brian Taba ,  Jennifer Klamo

IPC: G06N3/04 ,  G06F9/48 ,  G06F9/30 ,  G06N3/063

Abstract: Mapping of neural network layers to physical neural cores is provided. In various embodiments, a neural network description describing a plurality of neural network layers is read. Each of the plurality of neural network layers has an associated weight tensor, input tensor, and output tensor. A plurality of precedence relationships among the plurality of neural network layers is determined. The weight tensor, input tensor, and output tensor of each of the plurality of neural network layers are mapped onto an array of neural cores.

公开(公告)号：US20200019836A1

公开(公告)日：2020-01-16

申请号：US16033926

申请日：2018-07-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John V. Arthur ,  Andrew S. Cassidy ,  Myron D. Flickner ,  Pallab Datta ,  Hartmut Penner ,  Rathinakumar Appuswamy ,  Jun Sawada ,  Dharmendra S. Modha ,  Steven K. Esser ,  Brian Taba ,  Jennifer Klamo

IPC: G06N3/04 ,  G06N3/063

Abstract: Networks of distributed neural cores are provided with hierarchical parallelism. In various embodiments, a plurality of neural cores is provided. Each of the plurality of neural cores comprises a plurality of vector compute units configured to operate in parallel. Each of the plurality of neural cores is configured to compute in parallel output activations by applying its plurality of vector compute units to input activations. Each of the plurality of neural cores is assigned a subset of output activations of a layer of a neural network for computation. Upon receipt of a subset of input activations of the layer of the neural network, each of the plurality of neural cores computes a partial sum for each of its assigned output activations, and computes its assigned output activations from at least the computed partial sums.

公开(公告)号：US20200012929A1

公开(公告)日：2020-01-09

申请号：US16028158

申请日：2018-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hartmut Penner ,  Dharmendra S. Modha ,  John V. Arthur ,  Andrew S. Cassidy ,  Rathinakumar Appuswamy ,  Pallab Datta ,  Steven K. Esser ,  Myron D. Flickner ,  Jennifer Klamo ,  Jun Sawada ,  Brian Taba

IPC: G06N3/08 ,  G06N3/04 ,  G06N5/04

Abstract: Instruction distribution in an array of neural network cores is provided. In various embodiments, a neural inference chip is initialized with core microcode. The chip comprises a plurality of neural cores. The core microcode is executable by the neural cores to execute a tensor operation of a neural network. The core microcode is distributed to the plurality of neural cores via an on-chip network. The core microcode is executed synchronously by the plurality of neural cores to compute a neural network layer.

公开(公告)号：US20190251420A1

公开(公告)日：2019-08-15

申请号：US16391092

申请日：2019-04-22

Applicant: International Business Machines Corporation

Inventor： Rathinakumar Appuswamy ,  Myron D. Flickner ,  Dharmendra S. Modha

IPC: G06N3/04 ,  G06N3/063 ,  G06F17/16 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06F17/16 ,  G06N3/049 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088

Abstract: Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.

公开(公告)号：US10318862B2

公开(公告)日：2019-06-11

申请号：US15980612

申请日：2018-05-15

Applicant: International Business Machines Corporation

Inventor： Rathinakumar Appuswamy ,  Myron D. Flickner ,  Dharmendra S. Modha

IPC: G06N3/063 ,  G06N3/08

Abstract: Embodiments of the present invention provide a method for feature extraction comprising generating synaptic connectivity information for a neurosynaptic core circuit. The core circuit comprises one or more electronic neurons, one or more electronic axons, and an interconnect fabric including a plurality of synapse devices for interconnecting the neurons with the axons. The method further comprises initializing the interconnect fabric based on the synaptic connectivity information generated, and extracting a set of features from input received via the electronic axons. The set of features extracted comprises a set of features with reduced correlation.

公开(公告)号：US20190042886A1

公开(公告)日：2019-02-07

申请号：US16147106

申请日：2018-09-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Alexander Andreopoulos ,  Rathinakumar Appuswamy ,  Pallab Datta ,  Steven K. Esser ,  Dharmendra S. Modha

IPC: G06K9/62 ,  H04N9/67 ,  G06K9/46 ,  G06T7/246 ,  G06N3/08 ,  G06N3/063 ,  G06K9/66 ,  G06K9/52 ,  H04N19/136 ,  G06K9/00

Abstract: Embodiments of the invention provide a method for scene understanding based on a sequence of image frames. The method comprises converting each pixel of each image frame to neural spikes, and extracting features from the sequence of image frames by processing neural spikes corresponding to pixels of the sequence of image frames. The method further comprises encoding the extracted features as neural spikes, and classifying the extracted features.