公开(公告)号：US20210157963A1

公开(公告)日：2021-05-27

申请号：US16692129

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sean Michael Carey ,  Richard Frank Rizzolo ,  Bodo Hoppe ,  Divya Kumudprakash Joshi ,  Paul Jacob Logsdon ,  Sreekala Anandavally ,  WILLIAM RURIK

IPC: G06F30/3312

Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

公开(公告)号：US11501047B2

公开(公告)日：2022-11-15

申请号：US16692129

申请日：2019-11-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sean Michael Carey ,  Richard Frank Rizzolo ,  Bodo Hoppe ,  Divya Kumudprakash Joshi ,  Paul Jacob Logsdon ,  Sreekala Anandavally ,  William Rurik

IPC: G06F30/3312

Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.