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    ERROR INJECTION FOR TIMING MARGIN PROTECTION AND FREQUENCY CLOSURE
    3.
    发明申请
    ERROR INJECTION FOR TIMING MARGIN PROTECTION AND FREQUENCY CLOSURE 有权

    公开(公告)号：US20210157963A1

    公开(公告)日：2021-05-27

    申请号：US16692129

    申请日：2019-11-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Sean Michael Carey ,  Richard Frank Rizzolo ,  Bodo Hoppe ,  Divya Kumudprakash Joshi ,  Paul Jacob Logsdon ,  Sreekala Anandavally ,  WILLIAM RURIK

    IPC: G06F30/3312

    Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

    PROTECTING CHIP SETTINGS USING SECURED SCAN CHAINS
    7.
    发明申请
    PROTECTING CHIP SETTINGS USING SECURED SCAN CHAINS 有权
    使用安全扫描链保护芯片设置

    公开(公告)号：US20160070933A1

    公开(公告)日：2016-03-10

    申请号：US14944885

    申请日：2015-11-18

    Applicant: International Business Machines Corporation

    Inventor： Benedikt Geukes ,  Bodo Hoppe ,  Matteo Michel ,  Juergen Wakunda

    IPC: G06F21/72 ,  G06F21/76 ,  G01R31/3177

    CPC classification number: G06F21/72 ,  G01R31/31719 ,  G01R31/3177 ,  G01R31/318588 ,  G06F21/76

    Abstract: Some embodiments include a method for processing a scan chain in an integrated circuit, the method comprising receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; storing the scan chain in a first plurality of latches; storing the secret key pattern in a second plurality of latches; comparing the secret key pattern to a reference key pattern, the reference key pattern stored in a third plurality of latches; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

    Abstract translation: 一些实施例包括用于处理集成电路中的扫描链的方法，所述方法包括在所述集成电路中接收所述扫描链，其中所述扫描链包括秘密密钥图案; 将秘密密钥图案与扫描链分离; 将扫描链存储在第一多个锁存器中; 将所述秘密密钥图案存储在第二多个锁存器中; 将所述秘密密钥图案与参考密钥图案进行比较，所述参考密钥图案存储在第三多个锁存器中; 基于将所述秘密密钥图案与所述参考密钥图案进行比较来确定所述秘密密钥图案与所述参考密钥图案不匹配; 以及产生指示所述秘密密钥图案与所述参考键图案不匹配的信号。

    Error injection for timing margin protection and frequency closure
    8.
    发明授权
    Error injection for timing margin protection and frequency closure 有权

    公开(公告)号：US11501047B2

    公开(公告)日：2022-11-15

    申请号：US16692129

    申请日：2019-11-22

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Sean Michael Carey ,  Richard Frank Rizzolo ,  Bodo Hoppe ,  Divya Kumudprakash Joshi ,  Paul Jacob Logsdon ,  Sreekala Anandavally ,  William Rurik

    IPC: G06F30/3312

    Abstract: A non-limiting example of a computer-implemented method for error injection includes executing a pre-silicon operation on a simulated chip verifying that a plurality of latches from a timing simulation set error checkers when run against a manufacturing test suite in order to generate a cross-reference file containing latch entries in a table. It executes a first post-silicon operation on a hardware chip based on the simulated chip to determine empirically that timing latches from logic built-in self tests (“LBIST”) trigger the same error checkers set by the plurality of latches verified in the simulated chip. The method updates the cross-reference file based on the results of the determination. The method executes a second post-silicon operation on the hardware chip to improve chip frequency by working around functional checkers using the cross-reference file and updating the cross-reference file based on the results of the improving.

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