公开(公告)号：US11074184B2

公开(公告)日：2021-07-27

申请号：US16383705

申请日：2019-04-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael Cadigan, Jr. ,  Erez Barak ,  Deepankar Bhattacharjee ,  Yair Fried ,  Jonathan Hsieh ,  Martin Recktenwald ,  Aditya Nitin Puranik

IPC: G06F12/0815

Abstract: Methods, systems and computer program products for monitoring delivered packages are provided. Aspects include receiving, by a co-processor, a data stream and performing processing on the data stream. Aspects also include writing, by the co-processor, a data record into the output buffer. Based on a determination that the data record should replace a most recently stored data record in a cache, aspects include providing, by the co-processor to the cache controller, an instruction for the cache controller to write the data record to a location in the cache obtained from a most recently used address register. Based on a determination that the data record should not replace the most recently stored data record in the cache, aspects include writing, by the cache controller, the data record to an available location in the cache.

公开(公告)号：US11080199B2

公开(公告)日：2021-08-03

申请号：US16295117

申请日：2019-03-07

Applicant: International Business Machines Corporation

Inventor： Yossi Shapira ,  Jonathan Hsieh ,  Michael Cadigan, Jr. ,  Jane Bartik ,  Taylor J Pritchard

IPC: G06F12/0875 ,  G06F9/50 ,  G06F9/30 ,  G06F12/12

Abstract: Embodiments of the inventions are directed towards a computer-implemented methods and systems for determining an oldest logical memory address. The method includes creating an M number of miss request registers and an N number of stations in a load/store unit of the processor. In response to load requests from target instructions, a processor detects each L1 cache miss. The processor stores data related to each L1 cache miss in a respective miss request register. The data includes an age of each L1 cache miss and a portion of a logical memory address of the requested load. The processor stores the entire logical memory addresses of the requested loads in respective stations based on an age of the load requests. The processor transmits the oldest logical memory address that is stored at the stations.

公开(公告)号：US11243774B2

公开(公告)日：2022-02-08

申请号：US16359380

申请日：2019-03-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James Raymond Cuffney ,  Adam Collura ,  James Bonanno ,  Edward Malley ,  Anthony Saporito ,  Jang-Soo Lee ,  Michael Cadigan, Jr. ,  Jonathan Hsieh

IPC: G06F9/30 ,  G06F9/38

Abstract: Methods, systems and computer program products for dynamically selecting an OSC hazard avoidance mechanism are provided. Aspects include receiving a load instruction that is associated with an operand store compare (OSC) prediction. The OSC prediction is stored in an entry of an OSC history table (OHT) and includes a multiple dependencies indicator (MDI). Responsive to determining the MDI is in a first state, aspects include applying a first OSC hazard avoidance mechanism in relation to the load instruction. Responsive to determining that the load instruction is dependent on more than one store instruction, aspects include placing the MDI in a second state. The MDI being in the second state provides an indication to apply a second OSC hazard avoidance mechanism in relation to the load instruction.

公开(公告)号：US11150902B2

公开(公告)日：2021-10-19

申请号：US16272262

申请日：2019-02-11

Applicant: International Business Machines Corporation

Inventor： Taylor J. Pritchard ,  Jonathan Hsieh ,  Michael Cadigan, Jr.

IPC: G06F9/30 ,  G06F9/38

Abstract: Systems and methods of performing processor pipeline management include receiving an instruction for processing, determining that data in a first memory sub-group of a memory group needed to process the instruction is not available in a cache that ensures fixed latency access, and determining that the instruction should be put in a sleep state. The sleep state indicates that the instruction will not be reissued until the instruction is moved to a wakeup state. The methods also include associating the instruction with a ticket identifier (ID) that corresponds with a second memory sub-group of the memory group, and moving the instruction to the wakeup state based on the second memory sub-group of the memory group being moved into the cache.

公开(公告)号：US20200285583A1

公开(公告)日：2020-09-10

申请号：US16295117

申请日：2019-03-07

Applicant: International Business Machines Corporation

Inventor： Yossi Shapira ,  Jonathan Hsieh ,  Michael Cadigan, Jr. ,  Jane Bartik ,  Taylor J. Pritchard

IPC: G06F12/0875 ,  G06F12/12 ,  G06F9/30 ,  G06F9/50

Abstract: Embodiments of the inventions are directed towards a computer-implemented methods and systems for determining an oldest logical memory address. The method includes creating an M number of miss request registers and an N number of stations in a load/store unit of the processor. In response to load requests from target instructions, a processor detects each L1 cache miss. The processor stores data related to each L1 cache miss in a respective miss request register. The data includes an age of each L1 cache miss and a portion of a logical memory address of the requested load. The processor stores the entire logical memory addresses of the requested loads in respective stations based on an age of the load requests. The processor transmits the oldest logical memory address that is stored at the stations.