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1.发明申请FACETED INTRINSIC EPITAXIAL BUFFER LAYER FOR REDUCING SHORT CHANNEL EFFECTS WHILE MAXIMIZING CHANNEL STRESS LEVELS 有权面向内部外延缓冲层，用于在最大化通道应力水平时减少短路通道效应公开(公告)号：US20140264558A1
公开(公告)日：2014-09-18
申请号：US13839741
申请日：2013-03-15
发明人： Bhupesh Chandra , Paul Chang , Gregory G. Freeman , Dechao Guo , Judson R. Holt , Arvind Kumar , Timothy J. McArdle , Shreesh Narasimha , Viorel Ontalus , Sangameshwar Rao Saudari , Christopher D. Sheraw , Matthew W. Stoker
CPC分类号： H01L29/7848 , H01L29/045 , H01L29/165 , H01L29/36 , H01L29/66636 , H01L29/7834
摘要： A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.
摘要翻译： 通过选择性外延法将刻面的本征缓冲半导体材料沉积在源沟槽和漏极沟槽的侧壁上。 一个刻面邻接每个边缘，栅极间隔件的外侧壁邻接源沟槽或漏极沟槽的侧壁。 随后沉积掺杂的半导体材料以填充源极沟槽和漏极沟槽。 可以沉积掺杂的半导体材料，使得本征缓冲半导体材料的面被延伸，并且沉积的掺杂半导体材料的内壁在源极沟槽和漏极沟槽的每一个中融合。 掺杂的半导体材料随后可以向上生长。 方面的本征缓冲半导体材料部分允许在均匀宽度的区域中抑制掺杂剂的扩散，从而抑制短沟道效应，从而在小角部附近进一步扩散掺杂剂。
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2.发明授权Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels 有权方面的本征外延缓冲层，用于减少短通道效应，同时最大化通道应力水平公开(公告)号：US08940595B2
公开(公告)日：2015-01-27
申请号：US13839741
申请日：2013-03-15
发明人： Bhupesh Chandra , Paul Chang , Gregory G. Freeman , Dechao Guo , Judson R. Holt , Arvind Kumar , Timothy J. McArdle , Shreesh Narasimha , Viorel Ontalus , Sangameshwar Rao Saudari , Christopher D. Sheraw , Matthew W. Stoker
IPC分类号： H01L21/336 , H01L29/78 , H01L29/66
CPC分类号： H01L29/7848 , H01L29/045 , H01L29/165 , H01L29/36 , H01L29/66636 , H01L29/7834
摘要： A faceted intrinsic buffer semiconductor material is deposited on sidewalls of a source trench and a drain trench by selective epitaxy. A facet adjoins each edge at which an outer sidewall of a gate spacer adjoins a sidewall of the source trench or the drain trench. A doped semiconductor material is subsequently deposited to fill the source trench and the drain trench. The doped semiconductor material can be deposited such that the facets of the intrinsic buffer semiconductor material are extended and inner sidewalls of the deposited doped semiconductor material merges in each of the source trench and the drain trench. The doped semiconductor material can subsequently grow upward. Faceted intrinsic buffer semiconductor material portions allow greater outdiffusion of dopants near faceted corners while suppressing diffusion of dopants in regions of uniform width, thereby suppressing short channel effects.
摘要翻译： 通过选择性外延法将刻面的本征缓冲半导体材料沉积在源沟槽和漏极沟槽的侧壁上。 一个刻面邻接每个边缘，栅极间隔件的外侧壁邻接源沟槽或漏极沟槽的侧壁。 随后沉积掺杂的半导体材料以填充源极沟槽和漏极沟槽。 可以沉积掺杂的半导体材料，使得本征缓冲半导体材料的面被延伸，并且沉积的掺杂半导体材料的内壁在源极沟槽和漏极沟槽的每一个中融合。 掺杂的半导体材料随后可以向上生长。 方面的本征缓冲半导体材料部分允许在均匀宽度的区域中抑制掺杂剂的扩散，从而抑制短沟道效应，从而在小角部附近进一步扩散掺杂剂。
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