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公开(公告)号：US12094525B2
公开(公告)日：2024-09-17
申请号：US17814254
申请日：2022-07-22
IPC分类号： G11C11/4096 , G11C5/06 , G11C11/4093
CPC分类号： G11C11/4096 , G11C5/06 , G11C11/4093
摘要： A memory system, a method of assembling the memory system, and a computer system. The memory system includes a global memory device coupled to a plurality of processing elements. The global memory device is positioned external to a chip on which the plurality of processing devices reside. The memory system also includes at least one main scratchpad coupled to the at least one processing element of the plurality of processing devices and the global memory device. The memory system further includes a plurality of auxiliary scratchpads coupled to the plurality of processing elements and the global memory device. The one or more auxiliary scratchpads are configured to store static tensors. At least a portion of the plurality of auxiliary scratchpads are configured as a unitary multichannel device.
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公开(公告)号：US20240162192A1
公开(公告)日：2024-05-16
申请号：US17987823
申请日：2022-11-15
发明人： Arvind Kumar , Todd Edward Takken , John W Golz , Joshua M. Rubin
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
CPC分类号： H01L25/0657 , H01L24/16 , H01L24/17 , H01L25/0652 , H01L25/50 , H01L2224/16146 , H01L2224/16221 , H01L2224/17133 , H01L2224/17177 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06589 , H01L2924/14252 , H01L2924/1426 , H01L2924/1427 , H01L2924/1431 , H01L2924/1441 , H01L2924/1443 , H01L2924/1444 , H01L2924/30205
摘要： A semiconductor module includes a first semiconductor die, which comprises (i) a power support structure and (ii) a first cache region; and a second semiconductor die, which is mounted on top of the first semiconductor die and comprises (i) a logic core, which overlies and is electrically connected to the power support structure, and (ii) a second cache region, which overlies and is electrically connected to the first cache region.
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公开(公告)号：US11710669B2
公开(公告)日：2023-07-25
申请号：US16882624
申请日：2020-05-25
发明人： John Knickerbocker , Bing Dang , Qianwen Chen , Joshua M. Rubin , Arvind Kumar
IPC分类号： H01L21/66 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L22/20 , H01L25/0657 , H01L25/18 , H01L25/50 , H01L2225/06513 , H01L2225/06541
摘要： One or more die stacks are disposed on a redistribution layer (RDL) to make an electronic package. The die stacks include a die and one or more Through Silicon Via (TSV) dies. Other components and/or layers, e.g. interposes layers, can be included in the structure. An epoxy layer disposed on the RDL top surface and surrounds and attached to all the TSV die sides and all the die sides. Testing circuitry is located in various locations in some embodiments. Locations including in the handler, die, TSV dies, interposes, etc. Testing methods are disclosed, Methods of making including “die first” and “die last” methods are also disclosed. Methods of making heterogenous integrated structure and the resulting structures are also disclosed, particularly for large scale, e.g. wafer and panel size, applications.
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公开(公告)号：US11587890B2
公开(公告)日：2023-02-21
申请号：US16933549
申请日：2020-07-20
摘要： A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.
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5.发明授权公开(公告)号：US11501023B2
公开(公告)日：2022-11-15
申请号：US16862663
申请日：2020-04-30
发明人： Arvind Kumar , Takashi Ando , Dirk Pfeiffer
摘要： A technique relates to biasing, using a control system, a crossbar array of resistive processing units (RPUs) under a midrange condition, the midrange condition causing resistances of the RPUs to result in a random output of low values and high values in about equal proportions. The control system reinforces the low values and the high values of the random output by setting the resistances of the RPUs to a state that forces the low values and the high values having resulted from the midrange condition. Reinforcing the low values and the high values makes the random output permanent even when the crossbar array of the RPUs is not biased under the midrange condition. The control system records a sequence of the low values and the high values of the random output responsive to reinforcing the low values and the high values of the random output.
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公开(公告)号：US10986422B2
公开(公告)日：2021-04-20
申请号：US16196031
申请日：2018-11-20
发明人： Vijay Kumar Ananthapur Bache , Vijay Ekambaram , Bidhu R. Sahoo , Arvind Kumar , Padmanabha Venkatagiri Seshadri
IPC分类号： H04N21/858 , G06F40/30 , G06N20/00 , G06F3/01 , G06F40/284
摘要： A method and system for improving a hyper-video navigational process is provided. The method includes automatically tracking user exploration paths of users within a hyper video space comprising a video stream. Hotspot video frames are extracted from the hyper video space. Conversations associated with the user interactions are linked with spatial temporal regions of the hotspot video frames. Common attributes of the user exploration paths are associated with common aspects of the conversations and specified user view personas of the video stream are detected. Visual trajectory paths are extracted and a particular user persona is assigned to the hyper video space. In response, the hyper video space is automatically navigated.
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公开(公告)号：US10606738B2
公开(公告)日：2020-03-31
申请号：US15888376
申请日：2018-02-05
摘要： A blockchain test configuration may provide a simple and secure infrastructure for testing applications. One example method of operation may comprise one or more of transmitting a request to a network of nodes to test a test package associated with an application. The method may also include receiving results based on the test of the test package and recording the results in a blockchain.
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公开(公告)号：US10374048B2
公开(公告)日：2019-08-06
申请号：US15813314
申请日：2017-11-15
发明人： Anthony I. Chou , Arvind Kumar , Chung-Hsun Lin , Shreesh Narasimha , Claude Ortolland , Jonathan T. Shaw
IPC分类号： H01L29/423 , H01L29/51 , H01L21/265 , H01L29/66 , H01L21/28 , H01L21/02 , H01L21/426 , H01L21/8234 , H01L21/3115 , H01L21/324 , H01L29/40 , H01L21/84 , H01L29/78 , H01L21/283 , H01L21/3065 , H01L21/308 , H01L29/417
摘要： An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
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公开(公告)号：US10192161B1
公开(公告)日：2019-01-29
申请号：US15840125
申请日：2017-12-13
发明人： Babar Khan , Arvind Kumar , Yun Seog Lee , Ning Li , Devendra Sadana , Joel Pereira De Souza
摘要： Resistive processing unit including: a plurality of transistors each having a lithium-doped region, wherein the plurality of transistors are arranged in an array to provide resistance; at least one first transmission line electrically connected to a source region of each transistor in at least one column of the array; at least one second transmission line electrically connected to a drain region of each transistor in at least one row of the array; and at least one third transmission line electrically connected to a gate region of the plurality of transistors in at least one row of the array; wherein application of an electrical voltage to the at least one first transmission line, the at least one second transmission line or the at least one third transmission line mobilizes lithium ions in the lithium region, thereby affecting a channel resistance of at least one transistor in the plurality of transistors.
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公开(公告)号：US20190027535A1
公开(公告)日：2019-01-24
申请号：US15654282
申请日：2017-07-19
发明人： Arvind Kumar , Joshua M. Rubin
CPC分类号： H01L27/222 , G11C11/5607 , G11C2211/5615 , H01L27/228 , H01L43/02 , H01L43/12
摘要： A memory device includes a semiconductor device on a wafer. The semiconductor device includes a gate structure, a first source/drain region, and a second source/drain region. The gate structure is on the first side of the wafer. The first source/drain region is also on the first side of the wafer, and contacts a first end of the gate structure. The second source/drain region is on the second side of the wafer and extends into the first side to contact a second end of the gate structure. The memory device further includes a memory storage element on the second side of the wafer. The memory storage element contacts the second source/drain region.
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