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    Power-Scalable Skew Compensation in Source-Synchronous Parallel Interfaces
    1.
    发明申请
    Power-Scalable Skew Compensation in Source-Synchronous Parallel Interfaces 有权
    源同步并行接口中的功率可伸缩偏移补偿

    公开(公告)号：US20140140439A1

    公开(公告)日：2014-05-22

    申请号：US13683508

    申请日：2012-11-21

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Ankur Agrawal ,  Timothy O. Dickcson ,  Sergey Rylov

    IPC: H04L7/00

    CPC classification number: H04L25/14 ,  G06F1/10 ,  H04L7/0008 ,  H04L7/0025

    Abstract: A parallel receiver interface includes a plurality of parallel data receivers, each receiver receiving input data. A clock receiver is configured to receive a forwarded clock. A phase interpolator has an input coupled to the output of the clock receiver and has an output coupled to each of the parallel receivers. Parallel clock delay elements are within each of the parallel data receivers, each clock delay element configured to provide varying amounts of clock phase adjustment. Inputs of a multiplexer circuit within each of the parallel data receivers are coupled to the outputs of each of the parallel clock delay elements within a respective parallel data receiver. An output of the multiplexer circuit is coupled to a data sampler within the respective parallel data receiver, the multiplexer circuit being configured to be controlled by a logic signal.

    Abstract translation: 并行接收器接口包括多个并行数据接收器，每个接收器接收输入数据。 时钟接收器被配置为接收转发的时钟。 相位内插器具有耦合到时钟接收器的输出的输入，并且具有耦合到每个并行接收器的输出。 并行时钟延迟元件在每个并行数据接收器内，每个时钟延迟元件配置成提供不同量的时钟相位调整。 每个并行数据接收器内的多路复用器电路的输入耦合到相应的并行数据接收器内的每个并行时钟延迟元件的输出。 多路复用器电路的输出耦合到相应的并行数据接收器内的数据采样器，多路复用器电路被配置为由逻辑信号控制。

    METASTABILITY-FREE CLOCKLESS SINGLE FLUX QUANTUM LOGIC CIRCUITRY
    5.
    发明公开
    METASTABILITY-FREE CLOCKLESS SINGLE FLUX QUANTUM LOGIC CIRCUITRY 审中-公开

    公开(公告)号：US20240235558A9

    公开(公告)日：2024-07-11

    申请号：US17971700

    申请日：2022-10-24

    Applicant: International Business Machines Corporation

    Inventor： Sergey Rylov ,  John Francis Bulzacchelli ,  Matthew Beck

    IPC: H03K19/195 ,  H03K19/20

    CPC classification number: H03K19/195 ,  H03K19/20

    Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

    EFFECTIVE SYNCHRONOUS GATES FOR RAPID SINGLE FLUX QUANTUM LOGIC
    6.
    发明公开
    EFFECTIVE SYNCHRONOUS GATES FOR RAPID SINGLE FLUX QUANTUM LOGIC 审中-公开

    公开(公告)号：US20230351234A1

    公开(公告)日：2023-11-02

    申请号：US17733977

    申请日：2022-04-29

    Applicant: International Business Machines Corporation

    Inventor： Takeo Yasuda ,  Robert K. Montoye ,  Gerald W. Gibson ,  Sergey Rylov

    IPC: G06N10/20 ,  H03K19/195 ,  G06N10/40 ,  H03K19/096

    CPC classification number: G06N10/20 ,  H03K19/195 ,  G06N10/40 ,  H03K19/096

    Abstract: A superconducting multi-stage synchronous logic circuit structure includes a first clocked logic gate, a second clocked logic gate, and an unclocked logic gate. Each of the logic gates includes Josephson junctions. The first clocked logic gate has a single first clocked logic gate output; the second clocked logic gate has a single second clocked logic gate output. The unclocked logic gate has a first input connected in electrical communication with the first clocked logic gate output and has a second input connected in electrical communication with the second clocked logic gate output, and has a single output. The Josephson junctions of the unclocked logic gate are arranged such that, in a single clock cycle that drives the first clocked logic gate and the second clocked logic gate, the unclocked logic gate produces a single signal in response to the inputs of the first and second clocked logic gates.

    INTEGER MATRIX MULTIPLICATION BASED ON MIXED SIGNAL CIRCUITS
    7.
    发明申请
    INTEGER MATRIX MULTIPLICATION BASED ON MIXED SIGNAL CIRCUITS 有权

    公开(公告)号：US20220075596A1

    公开(公告)日：2022-03-10

    申请号：US17012916

    申请日：2020-09-04

    Applicant: International Business Machines Corporation

    Inventor： Ankur Agrawal ,  Martin Cochet ,  Jonathan E. Proesel ,  Sergey Rylov ,  Bodhisatwa Sadhu ,  Hyunkyu Ouh

    IPC: G06F7/544 ,  G06F7/523 ,  G06F7/50 ,  H03M1/68 ,  H03M1/46 ,  H03K19/20

    Abstract: A multiply-accumulate device comprises a digital multiplication circuit and a mixed signal adder. The digital multiplication circuit is configured to input L m1-bit multipliers and L m2-bit multiplicands and configured to generate N one-bit multiplication outputs, each one-bit multiplication output corresponding to a result of a multiplication of one bit of one of the L m1-bit multipliers and one bit of one of the L m2-bit multiplicands. The mixed signal adder comprises one or more stages, at least one stage configured to input the N one-bit multiplication outputs, each stage comprising one or more inner product summation circuits; and a digital reduction stage coupled to an output of a last stage of the one or more stages and configured to generate an output of the multiply-accumulate device based on the L m1-bit multipliers and the L m2-bit multiplicands.

    Metastability-free clockless single flux quantum logic circuitry
    9.
    发明授权
    Metastability-free clockless single flux quantum logic circuitry 有权

    公开(公告)号：US12231123B2

    公开(公告)日：2025-02-18

    申请号：US17971700

    申请日：2022-10-24

    Applicant: International Business Machines Corporation

    Inventor： Sergey Rylov ,  John Francis Bulzacchelli ,  Matthew Beck

    IPC: H03K19/195 ,  G06F1/10 ,  G06N10/20 ,  G06N10/40 ,  H03K19/20

    Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

    METASTABILITY-FREE CLOCKLESS SINGLE FLUX QUANTUM LOGIC CIRCUITRY
    10.
    发明公开
    METASTABILITY-FREE CLOCKLESS SINGLE FLUX QUANTUM LOGIC CIRCUITRY 审中-公开

    公开(公告)号：US20240137027A1

    公开(公告)日：2024-04-25

    申请号：US17971700

    申请日：2022-10-23

    Applicant: International Business Machines Corporation

    Inventor： Sergey Rylov ,  John Francis Bulzacchelli ,  Matthew Beck

    IPC: H03K19/195 ,  H03K19/20

    CPC classification number: H03K19/195 ,  H03K19/20

    Abstract: A device includes a logic circuit comprising a clockless single flux quantum logic gate which comprises a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and isolation buffer circuits. The output Josephson junction is coupled to an output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port, and a respective dynamic storage loop circuit and configured to absorb a circulating current of an antifluxon which is injected into the respective dynamic storage loop circuit to prevent the antifluxon from being output from the respective input port, and to inject a fluxon into the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port, and annihilate an antifluxon present in the respective dynamic storage loop circuit.

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