公开(公告)号：US20180203667A1

公开(公告)日：2018-07-19

申请号：US15406910

申请日：2017-01-16

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Tina BABINSKY ,  Udo KRAUTZ ,  Klaus M. KROENER ,  Silvia M. MUELLER ,  Andreas WAGNER

IPC分类号： G06F7/483 ,  G06F5/01

CPC分类号： G06F7/483 ,  G06F5/012 ,  G06F7/5443

摘要： A floating-point unit, configured to implement a fused-multiply-add operation on three 128 bit wide operands is provided, which includes a 113×113-bit multiplier; a left shifter; a right shifter; a select circuit including a 3-to-2 compressor; an adder connected to the dataflow from the select circuit; a first feedback path connecting a carry output of the adder to the select circuit; a second feedback path connecting the output of the adder to the shifters for passing an intermediate wide result through the shifters.