CAPACITIVE MEASUREMENTS OF DIVOTS IN SEMICONDUCTOR DEVICES
    1.
    发明申请
    CAPACITIVE MEASUREMENTS OF DIVOTS IN SEMICONDUCTOR DEVICES 有权
    半导体器件中的分辨率的电容测量

    公开(公告)号:US20160370311A1

    公开(公告)日:2016-12-22

    申请号:US14742917

    申请日:2015-06-18

    CPC classification number: H01L22/34 H01L22/14

    Abstract: Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a STI region and an active region. The approach also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The approach further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region.

    Abstract translation: 提供了表征浅沟槽隔离(STI)深度的方法。 该方法包括测量在衬底的第一区域处的第一电容,其中至少一个第一栅极线穿过STI区域和有源区域之间的边界结。 该方法还包括在衬底的第二区域处测量第二电容,其中至少一个第二栅极线与有源区交叉。 该方法还包括基于第一区域的第一电容和第二区域的第二电容之间的差来计算与第一区域处的纹路相关联的电容。

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