公开(公告)号：US20190198347A1

公开(公告)日：2019-06-27

申请号：US16288920

申请日：2019-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM ,  Robert R. ROBISON

IPC: H01L21/324 ,  H01L29/861 ,  H01L27/02 ,  H01L29/866

CPC classification number: H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

公开(公告)号：US20160370311A1

公开(公告)日：2016-12-22

申请号：US14742917

申请日：2015-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lyndon R. LOGAN ,  Edward J. NOWAK ,  Robert R. ROBISON ,  Yan HE

IPC: G01N27/22 ,  H01L23/64 ,  H01L29/06 ,  H01L21/66

CPC classification number: H01L22/34 ,  H01L22/14

Abstract: Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region of a substrate where at least one first gate line crosses over a boundary junction between a STI region and an active region. The approach also includes measuring a second capacitance at a second region of the substrate where at least one second gate line crosses over the active region. The approach further includes calculating a capacitance associated with a divot at the first region based on a difference between the first capacitance at the first region and the second capacitance at the second region.

Abstract translation: 提供了表征浅沟槽隔离（STI）深度的方法。 该方法包括测量在衬底的第一区域处的第一电容，其中至少一个第一栅极线穿过STI区域和有源区域之间的边界结。 该方法还包括在衬底的第二区域处测量第二电容，其中至少一个第二栅极线与有源区交叉。 该方法还包括基于第一区域的第一电容和第二区域的第二电容之间的差来计算与第一区域处的纹路相关联的电容。

公开(公告)号：US20160035717A1

公开(公告)日：2016-02-04

申请号：US14882549

申请日：2015-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM ,  Robert R. ROBISON

IPC: H01L27/02 ,  H01L29/861

CPC classification number: H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract translation: 为纳秒电脉冲退火工艺提供了结构和方法。 形成静电放电（ESD）N + / P +结构的方法包括在衬底上形成N +扩散和在衬底上形成P +扩散。 P +扩散与N +扩散电接触。 该方法还包括在N +扩散和P +扩散之间形成器件。 退火结构或材料的方法包括跨多个纳秒的静电放电（ESD）N + / P +结构施加电脉冲。

公开(公告)号：US20140124903A1

公开(公告)日：2014-05-08

申请号：US14154273

申请日：2014-01-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM ,  Robert R. ROBISON

IPC: H01L21/324 ,  H01L29/861

CPC classification number: H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

Abstract translation: 为纳秒电脉冲退火工艺提供了结构和方法。 形成静电放电（ESD）N + / P +结构的方法包括在衬底上形成N +扩散和在衬底上形成P +扩散。 P +扩散与N +扩散电接触。 该方法还包括在N +扩散和P +扩散之间形成器件。 退火结构或材料的方法包括跨多个纳秒的静电放电（ESD）N + / P +结构施加电脉冲。

公开(公告)号：US20180308708A1

公开(公告)日：2018-10-25

申请号：US16016920

申请日：2018-06-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, JR. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM ,  Robert R. ROBISON

IPC: H01L21/324 ,  H01L29/861 ,  H01L27/02 ,  H01L29/866

CPC classification number: H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an cathode on a substrate and a anode on the substrate. The anode is in electrical contact with the cathode. The method further includes forming a device between the cathode and the anode. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

公开(公告)号：US20160035716A1

公开(公告)日：2016-02-04

申请号：US14882548

申请日：2015-10-14

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michel J. ABOU-KHALIL ,  Robert J. GAUTHIER, Jr. ,  Tom C. LEE ,  Junjun LI ,  Souvick MITRA ,  Christopher S. PUTNAM ,  Robert R. ROBISON

IPC: H01L27/02 ,  H01L29/861

CPC classification number: H01L21/324 ,  H01L27/0255 ,  H01L29/8611 ,  H01L29/866

Abstract: Structures and methods are provided for nanosecond electrical pulse anneal processes. The method of forming an electrostatic discharge (ESD) N+/P+ structure includes forming an N+ diffusion on a substrate and a P+ diffusion on the substrate. The P+ diffusion is in electrical contact with the N+ diffusion. The method further includes forming a device between the N+ diffusion and the P+ diffusion. A method of annealing a structure or material includes applying an electrical pulse across an electrostatic discharge (ESD) N+/P+ structure for a plurality of nanoseconds.

公开(公告)号：US20150028397A1

公开(公告)日：2015-01-29

申请号：US13949609

申请日：2013-07-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Andres BRYANT ,  Lyndon R. LOGAN ,  Edward J. NOWAK ,  Robert R. ROBISON

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/78 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/66666 ,  H01L29/7841

Abstract: Approaches for zero capacitance memory cells are provided. A method of manufacturing a semiconductor structure includes forming a channel region by doping a first material with a first type of impurity. The method includes forming source/drain regions by doping a second material with a second type of impurity different than the first type of impurity, wherein the second material has a smaller bandgap than the first material. The method includes forming lightly doped regions between the channel region and the source/drain regions, wherein the lightly doped regions include the second material. The method includes forming a gate over the channel region, wherein the second material extends under edges of the gate.

Abstract translation: 提供零电容存储单元的方法。 制造半导体结构的方法包括通过掺杂第一种杂质的第一材料形成沟道区。 该方法包括通过用不同于第一种类型杂质的第二类型杂质掺杂第二材料来形成源极/漏极区域，其中第二材料具有比第一材料更小的带隙。 该方法包括在沟道区域和源极/漏极区域之间形成轻掺杂区域，其中轻掺杂区域包括第二材料。 该方法包括在通道区域上形成栅极，其中第二材料在栅极的边缘延伸。