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公开(公告)号：US08595391B1
公开(公告)日：2013-11-26
申请号：US12048588
申请日：2008-03-14
申请人： Ian D. Miller , Jorn W. Janneck , David B. Parlour
发明人： Ian D. Miller , Jorn W. Janneck , David B. Parlour
IPC分类号： G06F5/00
CPC分类号： G06F17/5054
摘要： Automatic queue sizing for data flow applications for an integrated circuit is described. Queue sizes for queues of a dataflow network are initialized to a set of first sizes for running as distributed actors without having to have centralized control. If it is determined there is a deadlock, causes for the dataflow network being deadlocked are analyzed with a controller coupled thereto to select a first actor thereof. The first actor of the dataflow network is selected as being in a stalled write phase state. Queue size is incremented for at least one queue of the queues to unlock the first actor from the stalled write phase state. The running, the determining, the analyzing, and the incrementing are iteratively repeated to provide a second set of sizes for the queue sizes sufficient to reduce likelihood of deadlock of the data flow network.
摘要翻译： 描述用于集成电路的数据流应用的自动队列大小。 数据流网络队列的队列大小被初始化为一组第一个大小，用于作为分布式角色进行运行，而无需集中控制。 如果确定存在死锁，则与其耦合的控制器分析数据流网络处于死锁状态的原因，以选择其第一actor。 数据流网络的第一个演员选择为处于停止的写入阶段状态。 对于至少一个队列队列，队列大小递增，以使第一个actor从停止的写入阶段状态解锁。 迭代地重复运行，确定，分析和递增，以为足以减少数据流网络死锁可能性的队列大小提供第二组大小。
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2.发明授权公开(公告)号：US08402164B1
公开(公告)日：2013-03-19
申请号：US12913626
申请日：2010-10-27
申请人： David B. Parlour , Jorn W. Janneck , Ian D. Miller
发明人： David B. Parlour , Jorn W. Janneck , Ian D. Miller
IPC分类号： G06F15/16
CPC分类号： G06F15/163 , G06F15/7825 , G06F15/7867
摘要： An asynchronous communication network in an integrated circuit is described. The asynchronous communication network comprises a plurality of circuit elements enabling the transmission of tokens, each circuit element having a component interface comprising: a routing network coupled to a first adjacent circuit element of the plurality of circuit elements; and a control circuit coupled to the routing network, the control circuit having a first input coupled to receive a first command requesting a detection of a token received at a second input of the control circuit, and a first acknowledgement output coupling a first acknowledgement signal indicating whether the first command is received at the first input. Methods of enabling asynchronous communication in an integrated circuit are also disclosed.
摘要翻译： 描述集成电路中的异步通信网络。 异步通信网络包括能够传送令牌的多个电路元件，每个电路元件具有组件接口，包括：耦合到多个电路元件中的第一相邻电路元件的路由网络; 以及耦合到所述路由网络的控制电路，所述控制电路具有耦合以接收请求检测在所述控制电路的第二输入处接收到的令牌的第一命令的第一输入和耦合指示的第一确认信号的第一确认输出 第一个命令是否在第一个输入接收。 还公开了在集成电路中实现异步通信的方法。
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3.发明授权Automated method of architecture mapping selection from constrained high level language description via element characterization 有权通过元素表征从约束高级语言描述中的自动化体系结构映射方法选择公开(公告)号：US08001510B1
公开(公告)日：2011-08-16
申请号：US12205825
申请日：2008-09-05
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Disclosure is made of approaches for mapping an electronic design specification to an implementation. In one approach, quality metrics are associated with functional units of the design, and the functional units are mapped to respective initial implementations. For each functional unit a respective quality indicator is determined based on the mapping. The quality indicator specifies a degree to which the functional unit achieves the associated quality metric. At least one of the functional units is selected for remapping based on the quality indicator of that functional unit or the quality indicator of another functional unit. An alternative implementation to the initial implementation is selected for each selected functional unit to improve the quality indicator. The selected functional unit is remapped to the selected alternative implementation.
摘要翻译： 披露了将电子设计规范映射到实现的方法。 在一种方法中，质量度量与设计的功能单元相关联，并且功能单元被映射到相应的初始实现。 对于每个功能单元，基于映射确定相应的质量指示符。 质量指标指定功能单元实现相关质量度量的程度。 基于该功能单元的质量指示符或另一功能单元的质量指示符，选择功能单元中的至少一个用于重新映射。 为每个所选择的功能单元选择初始实现的替代实现以改善质量指标。 所选择的功能单元被重新映射到所选择的替代实现。
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4.发明授权Method of generating data for estimating resource requirements for a circuit design 有权生成用于估计电路设计的资源需求的数据的方法公开(公告)号：US09117046B1
公开(公告)日：2015-08-25
申请号：US12041167
申请日：2008-03-03
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/5054 , G06F2217/72
摘要： A method of generating data for estimating resource requirements for a circuit design is disclosed. The method comprises identifying a plurality of intermediate circuit modules of netlists for circuit designs; elaborating each intermediate circuit module of the plurality of intermediate circuit modules according to an associated plurality of parameter sets; generating an estimate of resources for each intermediate circuit module and parameter set of the associated plurality of parameter sets; and storing the estimates of resources for the intermediate circuit modules.
摘要翻译： 公开了一种生成用于估计电路设计的资源需求的数据的方法。 该方法包括识别用于电路设计的网表的多个中间电路模块; 根据相关联的多个参数集详细描述多个中间电路模块的每个中间电路模块; 生成每个中间电路模块的资源估计和相关联的多个参数集的参数集合; 并存储用于中间电路模块的资源估计。
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5.发明授权Method and apparatus for processing an event notification in a concurrent processing system 有权在并发处理系统中处理事件通知的方法和装置公开(公告)号：US08572432B1
公开(公告)日：2013-10-29
申请号：US12417069
申请日：2009-04-02
申请人： David B. Parlour , Jorn W. Janneck , Ian D. Miller
发明人： David B. Parlour , Jorn W. Janneck , Ian D. Miller
CPC分类号： G06F11/0793 , G06F11/0712
摘要： In one embodiment, a concurrent processing system is disclosed. For example, in one embodiment of the present invention, a concurrent processing system, comprises a first processing element comprising a first monitor module, a second processing element in communication with the first processing element, the second processing element comprising a second monitor module, and a first system monitor for receiving a notification from at least one of: the first processing element, or the second processing element, wherein the notification indicates an event detected by one of the first monitor module, or the second monitor module.
摘要翻译： 在一个实施例中，公开了并发处理系统。 例如，在本发明的一个实施例中，并行处理系统包括第一处理单元，该第一处理单元包括第一监视器模块，与第一处理单元通信的第二处理单元，第二处理单元包括第二监视模块，以及 第一系统监视器，用于从以下中的至少一个接收通知：第一处理元件或第二处理元件，其中，所述通知指示由所述第一监视器模块或所述第二监视器模块之一检测到的事件。
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公开(公告)号：US08146040B1
公开(公告)日：2012-03-27
申请号：US12482687
申请日：2009-06-11
申请人： Jorn W. Janneck , David B. Parlour , Ian D. Miller
发明人： Jorn W. Janneck , David B. Parlour , Ian D. Miller
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A method of evaluating an architecture for an integrated circuit device is disclosed. The method comprises generating a library of primitives for a predetermined architecture; transforming an original dataflow program into an intermediate format; transforming the intermediate format to a dataflow program defined in terms of the predefined library of primitives; and generating an implementation profile comprising information related to an implementation of the original dataflow program in an integrated circuit having the predetermined architecture. A method of evaluating an architecture for an integrated circuit device is also disclosed.
摘要翻译： 公开了一种评估集成电路器件的架构的方法。 该方法包括生成用于预定体系结构的原语库; 将原始数据流程序转换为中间格式; 将中间格式转换为根据预定义的图元库定义的数据流程序; 以及生成包括与具有预定架构的集成电路中的原始数据流程序的实现有关的信息的实现简档。 还公开了一种评估集成电路器件的架构的方法。
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公开(公告)号：US07979835B1
公开(公告)日：2011-07-12
申请号：US12041182
申请日：2008-03-03
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method of estimating resource requirements for a circuit design is disclosed. The method comprises identifying intermediate circuit modules of a netlist associated with the circuit design; accessing a library of resource requirements for intermediate circuit modules of netlists for circuit designs; selecting intermediate circuit modules of the library according to predetermined parameters for the circuit design; and generating an estimate of resource requirements for the circuit design based upon resource requirements of the selected intermediate circuit modules.
摘要翻译： 公开了一种估计电路设计的资源需求的方法。 该方法包括识别与电路设计相关联的网表的中间电路模块; 访问电路设计网表的中间电路模块的资源需求库; 根据电路设计的预定参数选择库的中间电路模块; 以及基于所选择的中间电路模块的资源需求生成对电路设计的资源需求的估计。
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公开(公告)号：US07822886B1
公开(公告)日：2010-10-26
申请号：US12103995
申请日：2008-04-16
申请人： Ian D. Miller , Jorn W. Janneck , David B. Parlour
发明人： Ian D. Miller , Jorn W. Janneck , David B. Parlour
IPC分类号： G06F3/00
摘要： Dataflow control for an application with timing parameters, including interfacing temporal and non-temporal domains, is described. The domains receive input data to a first dataflow network block, which is processed for untimed output of first tokens. The first tokens are obtained by a memory interface for timed writing of data portions of the first tokens to data storage and for timed reading of the data portions therefrom. Sending of the data portions read to a first queue of a first controller block is untimed, and the data portions are output by the first controller block with physical timing parameters. Second tokens are generated by the first controller block responsive to the physical timing parameters. The second tokens are fed back to a second queue of the first dataflow network block to control rate of generation of the first tokens by the first dataflow network block.
摘要翻译： 描述了具有定时参数的应用的数据流控制，包括时间和非时域的接口。 这些域将输入数据接收到第一数据流网络块，其被处理以用于第一令牌的未定时输出。 通过存储器接口获得第一令牌，用于将第一令牌的数据部分定时写入数据存储器，并且用于定时读取数据部分。 读取到第一控制器块的第一队列的数据部分的发送被取消定时，并且数据部分由第一控制器块用物理定时参数输出。 响应于物理定时参数，第一控制器块产生第二令牌。 第二令牌被反馈到第一数据流网络块的第二队列，以控制由第一数据流网络块产生第一令牌的速率。
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9.发明授权Method and apparatus for supporting run-time reconfiguration in a programmable logic integrated circuit 有权用于支持可编程逻辑集成电路中的运行时重新配置的方法和装置公开(公告)号：US08402409B1
公开(公告)日：2013-03-19
申请号：US11373744
申请日：2006-03-10
CPC分类号： G06F17/5054 , G06F8/30 , G06F15/7871
摘要： Method and apparatus for generating an implementation of a program language circuit description for a programmable logic device (PLD) is described. In one example, the program language circuit description is analyzed to identify constructs indicative of dynamic function re-assignment. A hardware description of the program language circuit description is generated. The hardware description includes a plurality of implementations responsive to the identified constructs. Physical implementation data is generated from the hardware description. The physical implementation includes a plurality of partial configurations for the PLD based on the respective plurality of implementations in the hardware description.
摘要翻译： 描述了用于生成可编程逻辑器件（PLD）的程序语言电路描述的实现的方法和装置。 在一个示例中，分析程序语言电路描述以识别指示动态功能重新分配的构造。 生成程序语言电路描述的硬件描述。 硬件描述包括响应于所识别的构造的多个实现。 物理实现数据是从硬件描述生成的。 物理实现包括基于硬件描述中的相应多个实现的PLD的多个部分配置。
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10.发明授权Method and apparatus for designing a system for implementation in a programmable logic device 有权用于在可编程逻辑器件中设计用于实现的系统的方法和装置公开(公告)号：US07380232B1
公开(公告)日：2008-05-27
申请号：US11373709
申请日：2006-03-10
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Method and apparatus for designing a system for implementation in a programmable logic device (PLD) is described. In one example, a program language description of the system is captured. The program language description includes control code for configuring actor elements with functions to perform tasks in response to input data. A hardware implementation is generated for the PLD from the program language description by mapping the control code to decision logic, the functions to partial configuration streams, and the actor elements to reconfigurable slots.
摘要翻译： 描述了用于设计用于在可编程逻辑器件（PLD）中实现的系统的方法和装置。 在一个示例中，捕获系统的程序语言描述。 程序语言描述包括用于配置具有响应于输入数据执行任务的功能的actor元件的控制代码。 通过将控制代码映射到决策逻辑，部分配置流的功能和可配置时隙的actor元素，从程序语言描述生成PLD的硬件实现。
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