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1.发明授权Method and system for entry and verification of parasitic design constraints for analog integrated circuits 有权用于模拟集成电路寄生设计约束的输入和验证的方法和系统公开(公告)号：US08209650B2
公开(公告)日：2012-06-26
申请号：US12103961
申请日：2008-04-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5063
摘要： A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.
摘要翻译： 设计模拟集成电路（IC）的方法，寄生约束分析器和确定模拟IC的布局的方法符合寄生约束。 在一个实施例中，设计模拟IC的方法包括：（1）基于一组规范创建模拟集成电路的示意图，（2）将附加约束附加到原理图，（3）创建模拟 基于包括寄生约束的示意图的集成电路，（4）从布局的寄生元件提取寄生值，以及（5）将所提取的寄生值与寄生约束进行比较以验证其符合性。
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2.发明申请METHOD AND SYSTEM FOR ENTRY AND VERIFICATION OF PARASITIC DESIGN CONSTRAINTS FOR ANALOG INTEGRATED CIRCUITS 有权用于模拟集成电路的PARASITIC设计约束的输入和验证方法与系统公开(公告)号：US20090265672A1
公开(公告)日：2009-10-22
申请号：US12103961
申请日：2008-04-16
IPC分类号： G06F17/50
CPC分类号： G06F17/5063
摘要： A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.
摘要翻译： 设计模拟集成电路（IC）的方法，寄生约束分析器和确定模拟IC的布局的方法符合寄生约束。 在一个实施例中，设计模拟IC的方法包括：（1）基于一组规范创建模拟集成电路的示意图，（2）将附加约束附加到原理图，（3）创建模拟 基于包括寄生约束的示意图的集成电路，（4）从布局的寄生元件提取寄生值，以及（5）将所提取的寄生值与寄生约束进行比较以验证其符合性。
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