公开(公告)号：US20130021078A1

公开(公告)日：2013-01-24

申请号：US13188364

申请日：2011-07-21

申请人： Ilyas ELKIN ,  William James DALLY ,  Jonah M. ALBEN

发明人： Ilyas ELKIN ,  William James DALLY ,  Jonah M. ALBEN

IPC分类号： H03K3/01

CPC分类号： H03K3/356 ,  H03K3/356026 ,  H03K3/356052 ,  H03K3/356147 ,  H03K3/356191

摘要： One embodiment of the present invention sets forth a technique for capturing and holding a level of an input signal using a latch circuit that presents a low number of loads to the clock signal. The clock is only coupled to a bridging transistor and a pair of clock-activated pull-down or pull-up transistors. The level of the input signal is propagated to the output signal when the storage sub-circuit is not enabled. The storage sub-circuit is enabled by the bridging transistor and a propagation sub-circuit is activated and deactivated by the pair of clock-activated transistors.

摘要翻译： 本发明的一个实施例提出了一种使用向时钟信号呈现低负载的锁存电路来捕获和保持输入信号电平的技术。 时钟仅耦合到桥接晶体管和一对时钟激活的下拉或上拉晶体管。 当存储子电路未使能时，输入信号的电平被传播到输出信号。 存储子电路由桥接晶体管使能，传播子电路由一对时钟激活晶体管激活和去激活。