公开(公告)号：US09425772B2

公开(公告)日：2016-08-23

申请号：US13528725

申请日：2012-06-20

申请人： Wojciech Jakub Poppe ,  Ilyas Elkin ,  Puneet Gupta

发明人： Wojciech Jakub Poppe ,  Ilyas Elkin ,  Puneet Gupta

IPC分类号： H03K3/03 ,  G01R31/28

CPC分类号： H03K3/0315 ,  G01R31/2853

摘要： The described systems and methods can facilitate examination of device parameters including analysis of relatively dominant characteristic impacts on delays. In one embodiment, at least some coupling components (e.g., metal layer wires, traces, lines, etc.) have a relatively dominant impact on delays and the delay is in part a function of both capacitance and resistance of the coupling component. In one embodiment, a system comprises a plurality of dominant characteristic oscillating rings, wherein each respective one of the plurality of dominant characteristic oscillating rings includes a respective dominant characteristic. Additional analysis can be performed correlating the dominant characteristic delay impact results with device fabrication and operation.

摘要翻译： 所描述的系统和方法可以便于检查设备参数，包括对延迟的相对主导的特征影响的分析。 在一个实施例中，至少一些耦合部件（例如，金属层导线，迹线，线等）对延迟具有相对主要的影响，延迟部分地是耦合部件的电容和电阻的函数。 在一个实施例中，系统包括多个主要特征振荡环，其中多个主要特性振荡环中的每个相应的一个包括相应的主要特性。 可以进行附加分析，将主要特征延迟影响结果与器件制造和操作相关联。

公开(公告)号：US20130110437A1

公开(公告)日：2013-05-02

申请号：US13358387

申请日：2012-01-25

申请人： Abhishek Singh ,  Wojciech Jakub Poppe ,  Ilyas Elkin

发明人： Abhishek Singh ,  Wojciech Jakub Poppe ,  Ilyas Elkin

IPC分类号： G01R35/00 ,  G06F19/00

CPC分类号： G01K15/00 ,  G01R19/0084 ,  G01R35/005

摘要： A method, in one embodiment, can include modeling and calibrating two types of sensors that are part of a semiconductor device. In addition, the method can include determining a temperature and voltage based on data received from the two sensors.

摘要翻译： 在一个实施例中，一种方法可以包括建模和校准作为半导体器件的一部分的两种类型的传感器。 此外，该方法可以包括基于从两个传感器接收的数据来确定温度和电压。

公开(公告)号：US20130021107A1

公开(公告)日：2013-01-24

申请号：US13556129

申请日：2012-07-23

申请人： Wojciech Jakub Poppe ,  Puneet Gupta ,  Ilyas Elkin

发明人： Wojciech Jakub Poppe ,  Puneet Gupta ,  Ilyas Elkin

IPC分类号： H03K3/03

CPC分类号： H03K3/0315 ,  G01R31/2831 ,  G01R31/31725 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer. The plurality of vias from one metal layer to another metal layer can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map. The analysis component can include correlation of the via resistance into a wafer.

摘要翻译： 描述了组件特性分析系统和方法。 在一个实施例中，环形振荡器包括：可操作以引起信号转换的至少一个反转级; 具有对环形振荡器中的信号跃迁传播的增加的比较影响或影响的目标分量; 以及输出部件，用于输出目标部件对信号转换的影响的指示。 目标部件可以包括从一个金属层到另一个金属层的多个通孔。 从一个金属层到另一个金属层的多个通孔可以配置在电池中。 过孔可以对应于通孔层。 在一个示例性实现中，输出耦合到分析组件。 分析组件可以包括通孔电阻与晶片变化的相关性并产生晶片图。 分析组件可以包括通孔电阻与晶片的相关性。

公开(公告)号：US20080141088A1

公开(公告)日：2008-06-12

申请号：US11636748

申请日：2006-12-11

申请人： Ishwardutt Parulkar ,  Josephus C. Ebergen ,  Ilyas Elkin

发明人： Ishwardutt Parulkar ,  Josephus C. Ebergen ,  Ilyas Elkin

IPC分类号： G01R31/3181 ,  G06F11/26

CPC分类号： G01R31/318544 ,  G01R31/318594

摘要： A method and apparatus for test of asynchronous pipelines. An asynchronous data pipeline includes first and second pluralities of pipeline stages in an alternating sequence. Each of the pipeline stages includes a control circuit, a latch circuit configured to latch data responsive to an indication from the control circuit, and a combinational logic circuit coupled to receive data from an output of the latch circuit. Each of the latch circuits is scannable. The latch circuits of the first and second pluralities of pipeline stages form a data scan chain configured to load test data into the combinational logic circuits during testing of the data pipeline. The data pipeline further includes a control scan chain configured to load control data for operating the control circuits during testing of the data pipeline. Testing of the data pipeline can include independent testing of the control portion or the data portion.

摘要翻译： 一种用于异步管道测试的方法和装置。 异步数据流水线包括交替序列中的第一和第二多个流水线级。 每个流水线级包括控制电路，锁存电路，被配置为响应于来自控制电路的指示来锁存数据;以及组合逻辑电路，被耦合以从锁存电路的输出接收数据。 每个锁存电路都是可扫描的。 第一和第二多个流水线级的锁存电路形成数据扫描链，其配置为在测试数据管线期间将测试数据加载到组合逻辑电路中。 数据流水线还包括控制扫描链，其被配置为在测试数据流水线期间加载用于操作控制电路的控制数据。 数据管线的测试可以包括控制部分或数据部分的独立测试。

公开(公告)号：US09496853B2

公开(公告)日：2016-11-15

申请号：US13556129

申请日：2012-07-23

申请人： Wojciech Jakub Poppe ,  Puneet Gupta ,  Ilyas Elkin

发明人： Wojciech Jakub Poppe ,  Puneet Gupta ,  Ilyas Elkin

IPC分类号： H03K3/03 ,  G01R31/317 ,  H01L21/66 ,  G01R31/28

CPC分类号： H03K3/0315 ,  G01R31/2831 ,  G01R31/31725 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： Component characteristics analysis systems and methods are described. In one embodiment, a ring oscillator comprises: at least one inversion stage operable to cause a signal transition; a target component that has an increased comparative impact or influence on a signal transition propagation in the ring oscillator; and an output component for outputting an indication of the impact the target component has on the signal transition. The target component can include a plurality of vias from one metal layer to another metal layer, which can be configured in a cell. The vias can correspond to a via layer. In one exemplary implementation, the output is coupled to an analysis component. The analysis component can include correlation of the via resistance into a wafer variations and generate a wafer map and can include correlation of the via resistance into a wafer.

摘要翻译： 描述了组件特性分析系统和方法。 在一个实施例中，环形振荡器包括：可操作以引起信号转换的至少一个反转级; 具有对环形振荡器中的信号跃迁传播的增加的比较影响或影响的目标分量; 以及输出部件，用于输出目标部件对信号转换的影响的指示。 目标部件可以包括从一个金属层到另一个金属层的多个通孔，其可以配置在电池中。 过孔可以对应于通孔层。 在一个示例性实现中，输出耦合到分析组件。 分析组件可以包括通孔电阻与晶片变化的相关性并产生晶片图，并且可以包括通孔电阻与晶片的相关性。

公开(公告)号：US08952705B2

公开(公告)日：2015-02-10

申请号：US13287053

申请日：2011-11-01

申请人： Ilyas Elkin ,  Wojciech Jakub Poppe

发明人： Ilyas Elkin ,  Wojciech Jakub Poppe

IPC分类号： G01R27/28 ,  G01R31/30 ,  G01R31/28

CPC分类号： G01R31/2882 ,  G01R31/3016

摘要： Systems and methods for transition delay measuring are presented. A transition delay measuring method can include oscillating a signal between states and tracking an indication associated with an isolated attribute of the transitions between the states. Oscillations can include asymmetric transitions between the states and the tracked isolated attribute can be a delay in completing transitions between the states in one direction or vice versa. The asymmetric transitions can include transitions between the first state and the second state that are faster than slower transitions between the second state and the first state or vice versa. The tracked indication can be utilized in analysis of the isolated transition delay characteristics. The results can be utilized in analysis of various further features and characteristics (e.g., examination of leakage current related power consumption, timing of asymmetric operation, etc.). The analysis can include examination of fabrication process and operating parameters.

摘要翻译： 提出了用于过渡延迟测量的系统和方法。 转移延迟测量方法可以包括在状态之间振荡信号并且跟踪与状态之间的转换的隔离属性相关联的指示。 振荡可以包括状态之间的不对称转换，跟踪的隔离属性可以是在一个方向上完成状态之间的转换的延迟，反之亦然。 非对称转变可以包括在第一状态和第二状态之间的转变，其比第二状态和第一状态之间的较慢的转变更快，反之亦然。 跟踪的指示可以用于分析过渡延迟特性。 结果可用于分析各种其他特征和特性（例如，检查泄漏电流相关功率消耗，非对称操作的定时等）。 分析可以包括制造工艺和操作参数的检查。

公开(公告)号：US20140070847A1

公开(公告)日：2014-03-13

申请号：US13606582

申请日：2012-09-07

申请人： Ilyas Elkin ,  Ge Yang ,  Jonah Alben

发明人： Ilyas Elkin ,  Ge Yang ,  Jonah Alben

IPC分类号： H03K19/20 ,  H03K19/096

CPC分类号： H03K3/356026 ,  H03K19/0016

摘要： A clock gating latch, a method of gating a clock signal and an integrating circuit incorporating the clock gating latch or the method. In one embodiment, the clock gating latch includes: (1) a propagation circuit having a single, first switch configured to be driven by an input clock signal, (2) a keeper circuit coupled to the propagation circuit and having a single, first switch configured to be driven by the input clock signal and (3) an AND gate coupled to the propagation circuit and the keeper circuit and having an internal node coupled to a second switch in the propagation circuit and a second switch in the keeper circuit.

摘要翻译： 时钟门控锁存器，门控时钟信号的方法和结合时钟门控锁存器或该方法的积分电路。 在一个实施例中，时钟门控锁存器包括：（1）传播电路，其具有被配置为由输入时钟信号驱动的单个第一开关，（2）保持器电路，其耦合到所述传播电路并且具有单个第一开关 被配置为由输入时钟信号驱动，和（3）耦合到传播电路和保持器电路并具有耦合到传播电路中的第二开关的内部节点和保持器电路中的第二开关的与门。

公开(公告)号：US20130106438A1

公开(公告)日：2013-05-02

申请号：US13287053

申请日：2011-11-01

申请人： Ilyas Elkin ,  Wojciech Jakub Poppe

发明人： Ilyas Elkin ,  Wojciech Jakub Poppe

IPC分类号： G01R27/28

CPC分类号： G01R31/2882 ,  G01R31/3016

摘要： Systems and methods for transition delay measuring are presented. A transition delay measuring method can include oscillating a signal between states and tracking an indication associated with an isolated attribute of the transitions between the states. Oscillations can include asymmetric transitions between the states and the tracked isolated attribute can be a delay in completing transitions between the states in one direction or vice versa. The asymmetric transitions can include transitions between the first state and the second state that are faster than slower transitions between the second state and the first state or vice versa. The tracked indication can be utilized in analysis of the isolated transition delay characteristics. The results can be utilized in analysis of various further features and characteristics (e.g., examination of leakage current related power consumption, timing of asymmetric operation, etc.). The analysis can include examination of fabrication process and operating parameters.

摘要翻译： 提出了用于过渡延迟测量的系统和方法。 转移延迟测量方法可以包括在状态之间振荡信号并且跟踪与状态之间的转换的隔离属性相关联的指示。 振荡可以包括状态之间的不对称转换，跟踪的隔离属性可以是在一个方向上完成状态之间的转换的延迟，反之亦然。 非对称转变可以包括在第一状态和第二状态之间的转变，其比第二状态和第一状态之间的较慢的转变更快，反之亦然。 跟踪的指示可以用于分析过渡延迟特性。 结果可用于分析各种其他特征和特性（例如，检查泄漏电流相关功率消耗，非对称操作的定时等）。 分析可以包括制造工艺和操作参数的检查。

公开(公告)号：US08035425B2

公开(公告)日：2011-10-11

申请号：US12345009

申请日：2008-12-29

申请人： Robert P. Masleid ,  Ilyas Elkin

发明人： Robert P. Masleid ,  Ilyas Elkin

IPC分类号： H03B1/00

CPC分类号： H04B3/36 ,  H04B3/23 ,  H04L25/20

摘要： A repeater circuit. The repeater circuit includes two output circuits, two echo circuits, two activation circuits, and two deactivation circuits. Responsive to detecting a logical transition of an input signal, one of the activation circuits is configured to activate a corresponding output circuit, which is configured to drive an output signal on an output node. A corresponding echo circuit is configured to be activated and to drive an input node responsive to activation of the corresponding output circuit. A corresponding one of the deactivation circuits is configured to deactivate the corresponding output circuit after a delay time has elapsed, whereas the corresponding echo circuit is deactivated in response thereto. A keeper circuit is configured to continue providing the output signal on the output node after deactivation of the corresponding output circuit.

摘要翻译： 中继器电路。 中继器电路包括两个输出电路，两个回波电路，两个激活电路和两个去激活电路。 响应于检测输入信号的逻辑转换，激活电路之一被配置为激活相应的输出电路，其被配置为驱动输出节点上的输出信号。 相应的回波电路被配置为被激活并且响应于对应的输出电路的激活来驱动输入节点。 停用电路中的相应一个被配置为在延迟时间过去之后去激活相应的输出电路，而对应的回波电路则响应于此停用。 保持器电路被配置为在对应的输出电路去激活之后继续在输出节点上提供输出信号。

公开(公告)号：US07890826B2

公开(公告)日：2011-02-15

申请号：US11636748

申请日：2006-12-11

申请人： Ishwardutt Parulkar ,  Josephus C. Ebergen ,  Ilyas Elkin

发明人： Ishwardutt Parulkar ,  Josephus C. Ebergen ,  Ilyas Elkin

IPC分类号： G01R31/28 ,  H03K19/00

CPC分类号： G01R31/318544 ,  G01R31/318594

摘要： A method and apparatus for test of asynchronous pipelines. An asynchronous data pipeline includes first and second pluralities of pipeline stages in an alternating sequence. Each of the pipeline stages includes a control circuit, a latch circuit configured to latch data responsive to an indication from the control circuit, and a combinational logic circuit coupled to receive data from an output of the latch circuit. Each of the latch circuits is scannable. The latch circuits of the first and second pluralities of pipeline stages form a data scan chain configured to load test data into the combinational logic circuits during testing of the data pipeline. The data pipeline further includes a control scan chain configured to load control data for operating the control circuits during testing of the data pipeline. Testing of the data pipeline can include independent testing of the control portion or the data portion.

摘要翻译： 一种用于异步管道测试的方法和装置。 异步数据流水线包括交替序列中的第一和第二多个流水线级。 每个流水线级包括控制电路，锁存电路，被配置为响应于来自控制电路的指示来锁存数据;以及组合逻辑电路，被耦合以从锁存电路的输出接收数据。 每个锁存电路都是可扫描的。 第一和第二多个流水线级的锁存电路形成数据扫描链，其配置为在测试数据管线期间将测试数据加载到组合逻辑电路中。 数据流水线还包括控制扫描链，其被配置为在测试数据流水线期间加载用于操作控制电路的控制数据。 数据管线的测试可以包括控制部分或数据部分的独立测试。