公开(公告)号：US20190303511A1

公开(公告)日：2019-10-03

申请号：US16367493

申请日：2019-03-28

Applicant: Imagination Technologies Limited

Inventor： Robert McKemey ,  Sam Elliott ,  Emiliano Morini ,  Max Freiburghaus

IPC: G06F17/50

Abstract: Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

公开(公告)号：US11455451B2

公开(公告)日：2022-09-27

申请号：US16367493

申请日：2019-03-28

Applicant: Imagination Technologies Limited

Inventor： Robert McKemey ,  Sam Elliott ,  Emiliano Morini ,  Max Freiburghaus

IPC: G06F30/3323 ,  G06F30/33 ,  G06F119/18

Abstract: Methods and systems for verifying a hardware design for a component that implements a permutation respecting function. The methods include formally verifying that an instantiation of the hardware design produces the correct result to the function for a subset of the valid input vectors; and formally verifying that an instantiation of the hardware design is permutation respecting for each of one or more input vector permutations (i.e. that the instantiation of the hardware design produces the permutation related outputs for an input vector and the permutation of that input vector) over a set of input vectors. The subset and the input vector permutations are selected so that any valid input vector that is not in the subset can be generated from an input vector in the subset via a combination of the one or more input vector permutations.

公开(公告)号：US10796052B2

公开(公告)日：2020-10-06

申请号：US16675112

申请日：2019-11-05

Applicant: Imagination Technologies Limited

Inventor： Emiliano Morini ,  Sam Elliott

IPC: G06F17/50 ,  G06F30/3323 ,  G06F30/30 ,  G06F111/20

Abstract: Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q,r in response to any input pair N,D in a subset of non-negative input pairs. The one or more range reduction properties are configured to verify that if an instantiation of the integrated circuit hardware design will generate an output pair q,r in response to a non-negative input pair N,D then an instantiation of the integrated circuit hardware design to implement the integer divider will generate an output pair q′,r′ that has a predetermined relationship with q and r in response to another non-negative input pair N′,D where N and N′ have one of one or more predetermined relationships.

公开(公告)号：US20200074018A1

公开(公告)日：2020-03-05

申请号：US16675112

申请日：2019-11-05

Applicant: Imagination Technologies Limited

Inventor： Emiliano Morini ,  Sam Elliott

IPC: G06F17/50

Abstract: Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q,r in response to any input pair N,D in a subset of non-negative input pairs. The one or more range reduction properties are configured to verify that if an instantiation of the integrated circuit hardware design will generate an output pair q,r in response to a non-negative input pair N,D then an instantiation of the integrated circuit hardware design to implement the integer divider will generate an output pair q′,r′ that has a predetermined relationship with q and r in response to another non-negative input pair N′,D where N and N′ have one of one or more predetermined relationships.

公开(公告)号：US20180203953A1

公开(公告)日：2018-07-19

申请号：US15875176

申请日：2018-01-19

Applicant: Imagination Technologies Limited

Inventor： Emiliano Morini ,  Sam Elliott

IPC: G06F17/50

CPC classification number: G06F17/504 ,  G06F17/5045 ,  G06F2217/02

Abstract: Computer-implemented methods of verifying an integrated circuit hardware design to implement an integer divider wherein the integer divider is configured to receive a numerator N and a denominator D and output a quotient q and a remainder r. The method includes (a) verifying a base property is true for the integrated circuit hardware design and (b) formally verifying that one or more range reduction properties are true for the integrated circuit hardware design. The base property is configured to verify that an instantiation of the integrated circuit hardware design will generate a correct output pair q,r in response to any input pair N,D in a subset of non-negative input pairs. The one or more range reduction properties are configured to verify that if an instantiation of the integrated circuit hardware design will generate an output pair q,r in response to a non-negative input pair N,D then an instantiation of the integrated circuit hardware design to implement the integer divider will generate an output pair q′, r′ that has a predetermined relationship with q and r in response to another non-negative input pair N′,D where N and N′ have one of one or more predetermined relationships.