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公开(公告)号：US20150161058A1
公开(公告)日：2015-06-11
申请号：US14625719
申请日：2015-02-19
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
摘要翻译： 描述用于在数字信号处理系统中传送数据的技术。 在一个示例中，数字信号处理系统包括多个固定功能加速器，每个固定功能加速器均连接到存储器访问控制器，并且每个被配置为从存储器件读取数据，对数据执行一个或多个操作，并将数据写入存储器 设备。 为了避免将固定功能加速器硬连接在一起，并且为了提供可配置的数字信号处理系统，多线程处理器控制固定功能加速器和存储器之间的数据传输。 每个处理器线程被分配给存储器访问通道，并且线程被配置为检测事件的发生，并且响应于此，控制存储器访问控制器以使得所选择的固定功能加速器能够从数据读取数据或将数据写入到 存储器件通过其存储器访问通道。
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公开(公告)号：US20190220199A1
公开(公告)日：2019-07-18
申请号：US16363587
申请日：2019-03-25
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
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公开(公告)号：US08990522B2
公开(公告)日：2015-03-24
申请号：US13646649
申请日：2012-10-05
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
摘要翻译： 描述用于在数字信号处理系统中传送数据的技术。 在一个示例中，数字信号处理系统包括多个固定功能加速器，每个固定功能加速器均连接到存储器访问控制器，并且每个被配置为从存储器件读取数据，对数据执行一个或多个操作，并将数据写入存储器 设备。 为了避免将固定功能加速器硬连接在一起，并且为了提供可配置的数字信号处理系统，多线程处理器控制固定功能加速器和存储器之间的数据传输。 每个处理器线程被分配给存储器访问通道，并且线程被配置为检测事件的发生，并且响应于此，控制存储器访问控制器以使得所选择的固定功能加速器能够从数据读取数据或将数据写入到 存储器件通过其存储器访问通道。
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公开(公告)号：US20130111159A1
公开(公告)日：2013-05-02
申请号：US13646649
申请日：2012-10-05
IPC分类号： G06F12/08
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
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公开(公告)号：US10268377B2
公开(公告)日：2019-04-23
申请号：US15433888
申请日：2017-02-15
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
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公开(公告)号：US20170160947A1
公开(公告)日：2017-06-08
申请号：US15433888
申请日：2017-02-15
IPC分类号： G06F3/06
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
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公开(公告)号：US09575900B2
公开(公告)日：2017-02-21
申请号：US14625719
申请日：2015-02-19
CPC分类号： G06F3/0607 , G06F3/0629 , G06F3/0658 , G06F3/0673 , G06F9/3009 , G06F9/3851 , G06F9/5016 , G06F9/542 , G06F9/544 , G06F12/1081 , G06F13/28 , G06F2212/251
摘要： A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
摘要翻译： 描述用于在数字信号处理系统中传送数据的技术。 在一个示例中，数字信号处理系统包括多个固定功能加速器，每个固定功能加速器均连接到存储器访问控制器，并且每个被配置为从存储器件读取数据，对数据执行一个或多个操作，并将数据写入存储器 设备。 为了避免将固定功能加速器硬连接在一起，并且为了提供可配置的数字信号处理系统，多线程处理器控制固定功能加速器和存储器之间的数据传输。 每个处理器线程被分配给存储器访问通道，并且线程被配置为检测事件的发生，并且响应于此，控制存储器访问控制器以使得所选择的固定功能加速器能够从数据读取数据或将数据写入到 存储器件通过其存储器访问通道。
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