公开(公告)号：US11645042B2

公开(公告)日：2023-05-09

申请号：US17547071

申请日：2021-12-09

Applicant: Imagination Technologies Limited

Inventor： Jonas Kallen ,  Sam Elliott

IPC: G06F7/556 ,  G06F7/72 ,  G06F7/487

CPC classification number: G06F7/556 ,  G06F7/4873 ,  G06F7/727

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a:b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0:m]mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of ┌log 2M┐; and more than M−2u of the subset of modulo units are arranged at the maximal delay of ┌log 2M┐, where 2u is the power of 2 immediately smaller than M.

公开(公告)号：US11954456B2

公开(公告)日：2024-04-09

申请号：US18140571

申请日：2023-04-27

Applicant: Imagination Technologies Limited

Inventor： Jonas Kallen ,  Sam Elliott

IPC: G06F7/556 ,  G06F7/487 ,  G06F7/72

CPC classification number: G06F7/556 ,  G06F7/4873 ,  G06F7/727

Abstract: A binary logic circuit for determining the ratio x/d where x is a variable integer input, the binary logic circuit comprising: a logarithmic tree of modulo units each configured to calculate x[a: b]mod d for respective block positions a and b in x where b>a with the numbering of block positions increasing from the most significant bit of x up to the least significant bit of x, the modulo units being arranged such that a subset of M−1 modulo units of the logarithmic tree provide x[0: m]mod d for all m∈{1, M}, and, on the basis that any given modulo unit introduces a delay of 1: all of the modulo units are arranged in the logarithmic tree within a delay envelope of [log2 M]; and more than M−2u of the subset of modulo units are arranged at the maximal delay of [log2 M], where 2u is the power of 2 immediately smaller than M.