摘要:
A method and apparatus for reducing a Peak to Average Power Ratio (PAPR) using peak windowing is provided. In the apparatus, an absolute value calculator calculates an absolute value of an input signal, a subtractor subtracts a predetermined clipping threshold level from the absolute value, a smoothing unit performs smoothing on the subtracted signal according to a predetermined smoothing scheme and outputs a first smoothed signal, an adder adds the first smoothed signal to the clipping threshold level, an inverse calculator outputs a second smoothed signal by multiplying the clipping threshold level by an inverse of the added signal, and a multiplier outputs a final PAPR-reduced signal by multiplying the input signal by the second smoothed signal. The method and apparatus address an overcompensation problem while processing signals having a large bandwidth and a high data rate without delay, thereby minimizing the clipping influences on Bit Error Rate (BER) and Adjacent Channel Leakage Ratio (ACLR) performances.
摘要:
A method and apparatus for transmitting a signal in a Single Carrier-Frequency Division Multiplexing Access (SC-FDMA) communication system are provided. The method includes determining if a Bandwidth Expansion Factor (BEF) Q is an integer, the BEF being determined as N/M according to a number N of subcarriers of a system band and a number M of subcarriers of an allocated band, expanding an input signal to be transmitted Q times in a time domain when the Q is an integer, generating an SC-FDMA signal, and transmitting the SC-FDMA signal.
摘要:
A method and apparatus for block interleaving that eliminates the step of intermediary buffering. The method includes: (a) calculating a memory address at which first output data, of which number is equal to the number of rows of a first encoder is stored, (b) storing the first output data at the calculated memory address of a circular buffer, (c) storing second output data at an address which is incremented by a specific constant value from the calculated memory address of the circular buffer, and (d) storing (n+1)th output data at an address which is incremented by n from the calculated memory address of the circular buffer.