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公开(公告)号:US20180120916A1
公开(公告)日:2018-05-03
申请号:US15373466
申请日:2016-12-09
Applicant: Industrial Technology Research Institute
Inventor: Yung-Chieh Lin , Shih-Che Lin , Chao-Hong Chen , Liang-Chia Cheng
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3287
Abstract: A FPGA-based system power estimation apparatus and a method for estimating the power of a target intellectual property (IP) circuit are provided. The system power estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configured to accommodate the target IP circuit. The power analysis circuit is disposed into the FPGA. The power analysis circuit retrieves an internal operation-state signal of the target IP circuit. The power analysis circuit examines the internal operation-state signal to determine an operation state of the target IP circuit and uses a power model to convert the operation state of the target IP circuit into at least one power value.
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公开(公告)号:US10324517B2
公开(公告)日:2019-06-18
申请号:US15373466
申请日:2016-12-09
Applicant: Industrial Technology Research Institute
Inventor: Yung-Chieh Lin , Shih-Che Lin , Chao-Hong Chen , Liang-Chia Cheng
IPC: G06F1/32 , G06F1/324 , G06F1/3287
Abstract: A FPGA-based system power estimation apparatus and a method for estimating the power of a target intellectual property (IP) circuit are provided. The system power estimation apparatus includes a FPGA and a power analysis circuit. The FPGA is configured to accommodate the target IP circuit. The power analysis circuit is disposed into the FPGA. The power analysis circuit retrieves an internal operation-state signal of the target IP circuit. The power analysis circuit examines the internal operation-state signal to determine an operation state of the target IP circuit and uses a power model to convert the operation state of the target IP circuit into at least one power value.
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公开(公告)号:US11537893B2
公开(公告)日:2022-12-27
申请号:US16729480
申请日:2019-12-30
Applicant: Industrial Technology Research Institute
Inventor: Ming-Chun Hsyu , Chao-Hong Chen , Chien-Chih Huang
Abstract: A method and an electronic device for selecting deep neural network hyperparameters are provided. In an embodiment of the method, a plurality of testing hyperparameter configurations are sampled from a plurality of hyperparameter ranges of a plurality of hyperparameters. A target neural network model is trained by using a training dataset and the plurality of testing hyperparameter configurations, and a plurality of accuracies corresponding to the plurality of testing hyperparameter configurations are obtained after training for preset epochs. A hyperparameter recommendation operation is performed to predict a plurality of final accuracies of the plurality of testing hyperparameter configurations. A recommended hyperparameter configuration corresponding to the final accuracy having a highest predicted value is selected as a hyperparameter setting for continuing training the target neural network model.
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公开(公告)号:US20210174210A1
公开(公告)日:2021-06-10
申请号:US16729480
申请日:2019-12-30
Applicant: Industrial Technology Research Institute
Inventor: Ming-Chun Hsyu , Chao-Hong Chen , Chien-Chih Huang
Abstract: A method and an electronic device for selecting deep neural network hyperparameters are provided. In an embodiment of the method, a plurality of testing hyperparameter configurations are sampled from a plurality of hyperparameter ranges of a plurality of hyperparameters. A target neural network model is trained by using a training dataset and the plurality of testing hyperparameter configurations, and a plurality of accuracies corresponding to the plurality of testing hyperparameter configurations are obtained after training for preset epochs. A hyperparameter recommendation operation is performed to predict a plurality of final accuracies of the plurality of testing hyperparameter configurations. A recommended hyperparameter configuration corresponding to the final accuracy having a highest predicted value is selected as a hyperparameter setting for continuing training the target neural network model.
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